AD7143 Datasheet, PDF (34/56 Pages) Analog Devices – Programmable Controller for Capacitance Touch Sensors

AD7143
REGISTER MAP
The AD7143 address space is divided into three different
register banks, referred to as Bank 1, Bank 2, and Bank 3.
Figure 47 illustrates the division of these three banks.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Bank 2 registers contain the configuration registers used for
uniquely configuring the CIN inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
Bank 3 registers contains the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7143 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power up and configuration of the Bank 2
registers.
ADDR 0x000
ADDR 0x001
ADDR 0x005
ADDR 0x008
ADDR 0x00B
ADDR 0x013
ADDR 0x017
ADDR 0x018
ADDR 0x042
ADDR 0x043
REGISTER BANK 1
SET UP CONTROL
(1 REGISTER)
CALIBRATION AND SET UP
(4 REGISTERS)
INTERRUPT ENABLE
(3 REGISTERS)
INTERRUPT STATUS
(3 REGISTERS)
CDC 16-BIT CONVERSION DATA
(8 REGISTERS)
UNUSED (4 REGISTERS)
DEVICE ID REGISTER
INVALID DO NOT ACCESS
PROXIMITY STATUS REGISTER
ADDR 0x080
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0B8
REGISTER BANK 2
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE1 CONFIGURATION
(8 REGISTERS)
STAGE2 CONFIGURATION
(8 REGISTERS)
STAGE3 CONFIGURATION
(8 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
STAGE6 CONFIGURATION
(8 REGISTERS)
STAGE7 CONFIGURATION
(8 REGISTERS)
ADDR 0x0E0
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x7F0
INVALID DO NOT ACCESS
Figure 47. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
REGISTER BANK 3
STAGE0 RESULTS
(36 REGISTERS)
STAGE1 RESULTS
(36 REGISTERS)
STAGE2 RESULTS
(36 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
STAGE4 RESULTS
(36 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
STAGE6 RESULTS
(36 REGISTERS)
STAGE7 RESULTS
(36 REGISTERS)
Rev. 0 | Page 34 of 56