ADUC824 Datasheet, PDF (33/68 Pages) Analog Devices – MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU

PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE
Tables IX, X, and XI below show the output rms noise in µV
and output peak-to-peak resolution in bits (rounded to the
nearest 0.5 LSB) for some typical output update rates on both
the Primary and Auxiliary ADCs. The numbers are typical and
ADuC824
are generated at a differential input voltage of 0 V. The output
update rate is selected via the SF7–SF0 bits in the Sinc Filter
(SF) SFR. It is important to note that the peak-to-peak resolu-
tion figures represent the resolution for which there will be no
code flicker within a six-sigma limit.
SF
Word
13
69
255
Table IX. Primary ADC, Typical Output RMS Noise (␮V)
Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in ␮V
Data Update
Rate (Hz)
105.3
19.79
5.35
؎20 mV
1.50
0.60
0.35
؎40 mV
1.50
0.65
0.35
؎80 mV
1.60
0.65
0.37
Input Range
؎160 mV
1.75
0.65
0.37
؎320 mV
3.50
0.65
0.37
؎640 mV
4.50
0.95
0.51
؎1.28 V
6.70
1.40
0.82
؎2.56 V
11.75
2.30
1.25
SF
Word
13
69
255
Table X. Primary ADC, Peak-to-Peak Resolution (Bits)
Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits
Data Update
Rate (Hz)
105.3
19.79
5.35
؎20 mV
12
13
14
؎40 mV
13
14
15
؎80 mV
14
15
16
Input Range
؎160 mV
15
16
17
؎320 mV
15
17
18
؎640 mV
15.5
17.5
18.5
؎1.28 V
16
18
18.8
؎2.56 V
16
18.5
19.2
Table XI. Auxiliary ADC
Typical Output RMS Noise vs. Update Rate*
Output RMS Noise in ␮V
Peak-to-Peak Resolution vs. Update Rate¹
Peak-to-Peak Resolution in Bits
SF
Word
Data Update
Rate (Hz)
13
105.3
69
19.79
255
5.35
*ADC converting in bipolar mode.
Input Range
2.5 V
10.75
2.00
1.15
SF
Word
13
69
255
Data Update
Rate (Hz)
105.3
19.79
5.35
Input Range
2.5 V
16²
16
16
NOTES
1_{ADC converting in bipolar mode.}
2_{In unipolar mode peak-to-peak resolution at 105 Hz is 15 bits.}
Analog Input Channels
The primary ADC has four associated analog input pins (labelled
AIN1 to AIN4) that can be configured as two fully differential
input channels. Channel selection bits in the ADC0CON SFR
detailed in Table V allow three combinations of differential pair
selection as well as an additional shorted input option (AIN2–AIN2).
The auxiliary ADC has three external input pins (labelled AIN3
to AIN5) as well as an internal connection to the internal on-chip
temperature sensor. All inputs to the auxiliary ADC are single-
ended inputs referenced to the AGND on the part. Channel
selection bits in the ADC1CON SFR detailed previously in
Table VI allow selection of one of four inputs.
Two input multiplexers switch the selected input channel to the
on-chip buffer amplifier in the case of the primary ADC and
directly to the sigma-delta modulator input in the case of the
auxiliary ADC. When the analog input channel is switched, the
settling time of the part must elapse before a new valid word is
available from the ADC.
Primary and Auxiliary ADC Inputs
The output of the primary ADC multiplexer feeds into a high
impedance input stage of the buffer amplifier. As a result, the
primary ADC inputs can handle significant source impedances and
are tailored for direct connection to external resistive-type sensors
like strain gauges or Resistance Temperature Detectors (RTDs).
The auxiliary ADC, however, is unbuffered, resulting in higher
analog input current on the auxiliary ADC. It should be noted that
this unbuffered input path provides a dynamic load to the driving
source. Therefore, resistor/capacitor combinations on the input
pins can cause dc gain errors depending on the output impedance
of the source that is driving the ADC inputs.
Analog Input Ranges
The absolute input voltage range on the primary ADC is restricted
to between AGND + 100 mV to AVDD – 100 mV. Care must be
taken in setting up the common-mode voltage and input voltage
range so that these limits are not exceeded, otherwise there will
be a degradation in linearity performance.
REV. B
–33–