ADSP-2104L_15 Datasheet, PDF (33/36 Pages) Analog Devices – Low Cost DSP Microcomputers

TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
SERIAL PORTS
Parameter
Timing Requirement:
t_SCK SCLK Period
t_SCS DR/TFS/RFS Setup before SCLK Low
t_SCH DR/TFS/RFS Hold after SCLK Low
t_SCP
SCLK_in Width
Switching Characteristic:
t_CC
t_SCDE
t_SCDV
t_RH
t_RD
t_SCDH
t_TDE
t_TDV
t_SCDD
t_RDV
CLKOUT High to SCLK_out
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFS_out Hold after SCLK High
TFS/RFS_out Delay from SCLK High
DT Hold after SCLK High
TFS (alt) to DT Enable
TFS (alt) to DT Valid
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero)
to DT Valid
13.824 MHz
Min Max
72.3
8
10
28
18.1 33.1
0
20
0
20
0
0
18
25
20
ADSP-2104/ADSP-2109
Frequency
Dependency
Min
Max
0.25t_CK
0.25t_CK + 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
SCLK
DR
RFSIN
TFSIN
RFSOUT
TFSOUT
DT
TFS
( ALTERNATE
FRAME MODE )
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
t_CC
t_RD
t_RH
t_SCDV
t_SCDE
t_TDE
t_TDV
t_CC
t_SCS t_SCH
t_SCK
t_SCP
t_SCP
t_SCDH
t_SCDD
t_RDV
Figure 30. Serial Ports
REV. 0
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