AD6657A Datasheet, PDF (33/36 Pages) Analog Devices – Quad IF Receiver

Data Sheet
AD6657A
Addr. Register
(Hex) Name
(MSB)
Bit 7
0x24 BIST
signature LSB
(local)
0x25 BIST signa-
ture MSB
(local)
Digital Feature Control Registers
0x3A Sync control Open
(global)
Bit 6
Open
0x3C NSR control
(local)
Open
Open
0x3E NSR tuning
word
(local)
Open
Open
Bit 5
Bit 4
Bit 3
Bit 2
BIST Signature[7:0]
BIST Signature[15:8]
Default
(LSB)
Value
Bit 1
Bit 0
(Hex) Comments
0x00
Read only.
0x00
Read only.
Open
Open
Open
Open
Clock divider
sync mode
0 = conti-
nuous
1 = next sync
mode, next
rising edge of
sync resets
clock divider
Clock
divider
sync
enable
0 = off
1 = on
Master
sync
enable
0 = off
1 = on
MODE
pin
disable
0=
MODE
pin used
1=
MODE
pin dis-
abled
NSR mode
000 = 22% BW mode
001 = 33% BW mode
010 = 36% BW mode
NSR
enable
0 = off
1 = on
(used only
if
Bit 4 = 1;
otherwise
ignored)
NSR tuning word
See the Noise Shaping Requantizer section.
Equations for the tuning word are dependent on the NSR mode.
0x00
0x00
0x1C
Control
register to
synchronize
the clock
divider.
Noise
shaping
requantizer
(NSR)
controls.
NSR
frequency
tuning word.
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled
in Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
Bit 2—Clock Divider Sync Mode
Bit 2 selects the mode of the clock divider sync function. When
Bit 2 is low, continuous sync mode is enabled. When Bit 2 is
high, the clock divider is reset on the next rising edge of the
sync signal. Subsequent rising edges of the sync signal are
ignored.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If
the sync capability is not used, this bit should remain low
to conserve power.
NSR Control (Register 0x3C)
Bits[7:5]—Reserved
Bit 4—MODE Pin Disable
Bit 4 specifies whether the selected channels are to be controlled
by the MODE pin. Local registers act on the channels that are
selected by the channel index register (Address 0x05).
Bits[3:1]—NSR Mode
Bits[3:1] determine the bandwidth (BW) mode of the NSR.
When Bits[3:1] are set to 000, the NSR is configured for a 22%
BW mode that provides enhanced SNR performance over 22%
of the sample rate. When Bits[3:1] are set to 001, the NSR is
configured for a 33% BW mode that provides enhanced SNR
performance over 33% of the sample rate. When Bits[3:1] are
set to 010, the NSR is configured for a 36% BW mode that pro-
vides enhanced SNR performance over 36% of the sample rate.
Bit 0—NSR Enable
The NSR is enabled when Bit 0 is high and disabled when Bit 0
is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4)
is set.
Rev. 0 | Page 33 of 36