ADSP-21367_06 Datasheet, PDF (32/56 Pages) Analog Devices – SHARC Processors

ADSP-21367/ADSP-21368/ADSP-21369
Asynchronous Memory Interface (AMI) Enable/Disable
Use these specifications for passing bus mastership between
ADSP-21368 processors (BRx).
Table 27. AMI Enable/Disable
Parameter
Switching Characteristics
t_ENAMIAC
t_ENAMID
t_DISAMIAC
t_DISAMID
Address/Control Enable After Clock Rise
Data Enable After Clock Rise
Address/Control Disable After Clock Rise
Data Disable After Clock Rise
Min
4
t_SCLK + 4
Max
8.7
0
Unit
ns
ns
ns
ns
CLKIN
ADDR, WR, RD,
MS1-0, DATA
ADDR, WR, RD,
MS1-0, DATA
t_DISAMIAC
t_{DIS AM ID}
t_ENAMIAC
t_{EN AMID}
Figure 20. AMI Enable/Disable
Rev. A | Page 32 of 56 | August 2006