AD8362 Datasheet, PDF (32/36 Pages) Analog Devices – 50 Hz to 2.7 GHz 60 dB TruPwr™ Detector

AD8362
AD8362 EVALUATION BOARD
The AD8362 evaluation board provides for a number of
different operating modes and configurations, including many
of those described in this data sheet. The measurement mode is
set up by positioning SW2 as shown in Figure 69. The AD8362
can be operated in controller mode by flipping SW2 to its
alternate position, thereby connecting the VSET pin to the
VSET connector and applying the setpoint voltage to the VSET
connector.
The internal voltage reference is used for the target voltage
when SW1 is in the position shown in Figure 69. This voltage
may optionally be reduced via a voltage divider implemented
with R4 and R5, with LK1 in place as shown in Figure 69 and
SW1 switched to its alternate position. Alternatively, an external
target voltage may be used with SW1 switched to its alternate
position, LK1 removed, and the external target voltage applied
to the VTGT connector.
In measurement mode, the slope of the response at VOUT may
be increased through the use of a voltage divider implemented
with the appropriately valued resistors, as explained in this data
sheet, in Positions R17 and R9, and with SW2 switched to its
alternate position.
The AD8362 is powered up with SW3 in the position shown in
Figure 69 and connector PWDN open. The part can be powered
down either by connecting a logic high voltage to connector
PWDN with SW3 in the position shown in Figure 69 or by
switching SW3 to its alternate position.
Balun Transformer T1 may be removed and replaced by two
capacitors and an inductor, as shown in Figure 54, or by two 0 Ω
resistors (links, size 0402): one in series with Capacitors C6 and
C10, and the other in series with C5 and a 100 Ω resistor installed
in Position R16, to implement the circuit shown in Figure 53.
AGND
VPOS
C1
0.1µF
R1
0Ω
C2
100pF
RFIN
C10
1000pF
PDWN
R14
OPEN
R15
0Ω
C8
1000pF
C7
1000pF
T1
C6
100pF
SW3
R16
OPEN
C5
100pF
C4
1000pF
R13
10kΩ
AD8362
1 COMM
ACOM 16
2 CHPF
VREF 15
3 DECL
VTGT 14
4 INHI
VPOS 13
5 INLO
VOUT 12
6 DECL
VSET 11
7 PWDN
ACOM 10
8 COMM
CLPF 9
R4
0Ω
VREF
R5
SW1 ^10kΩ LK1
R6
0Ω
VTGT
R17 R8
OPEN ^0Ω
R7
SW2
0Ω
R9
10kΩ _C3
0.1µF
R10
0Ω
C9
OPEN
VOUT
VSET
Figure 69. Evaluation Board Schematic
Rev. B | Page 32 of 36