AD5124 Datasheet, PDF (32/36 Pages) Analog Devices – The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.

AD5124/AD5144/AD5144A
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
AD5124:
R_WB (D)

D
128

R_AB

R_W
AD5144/AD5144A:
From 0x00 to 0x7F (5)
R_WB
(D)

D
256

R _AB

R_W
From 0x00 to 0xFF (6)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B to the maximum continuous
current of ±6 mA or to the pulse current specified in Table 7.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 47.
V_A
A
W
V_OUT
B
V_B
Figure 47. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
V_W (D)

R_WB (D)
R_AB
V_A

R_AW (D)
R_AB
V_B
(7)
where:
RWB(D) can be obtained from Equation 1 and Equation 2.
RAW(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode results
in a more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent mainly on the
ratio of the internal resistors, RAW and RWB, and not the absolute
values. Therefore, the temperature drift reduces to 5 ppm/°C.
Data Sheet
TERMINAL VOLTAGE OPERATING RANGE
The AD5124/AD5144/AD5144A are designed with internal ESD
diodes for protection. These diodes also set the voltage boundary
of the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
V_DD
A
W
B
V_SS
Figure 48. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 48), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and
VA, VB, and VW. The order of powering VA, VB, VW, and digital
inputs is not important as long as they are powered after VSS,
VDD, and VLOGIC. Regardless of the power-up sequence and the
ramp rates of the power supplies, once VDD is powered, the
power-on preset activates, which restores EEPROM values to
the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 49 illustrates the basic supply bypassing configuration
for the AD5124/AD5144/AD5144A.
V_{DD + C3}
10µF
+ _C4
10µF
V_SS
C1
0.1µF
C2
0.1µF
V_DD V_LOGIC
AD5124/
AD5144/
AD5144A
V_SS
GND
+ _C5
0.1µF
C6
10µF
V_LOGIC
Figure 49. Power Supply Bypassing
Rev. A | Page 32 of 36