ADSP-BF538_08 Datasheet, PDF (31/56 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF538/ADSP-BF538F
Table 21. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Min
Timing Requirements
t_DANR
ARDY Negated Delay from AMSx Asserted¹
t_HAA
ARDY Asserted Hold After ARE Negated
0.0
Switching Characteristics
t_DDAT
DATA15–0 Disable After CLKOUT
t_ENDAT
DATA15–0 Enable After CLKOUT
1.0
t_DO
Output Delay After CLKOUT²
t_HO
Output Hold After CLKOUT²
0.8
1 _{S = number of programmed setup cycles, WA = number of programmed write access cycles.}
2 _{Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.}
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
HOLD
1 CYCLE
Max
Unit
(S + WA – 2) × t_SCLK ns
ns
6.0
ns
ns
6.0
ns
ns
CLKOUT
t _DO
t _HO
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA15–0
t_DO
t_DANW
BE, ADDRESS
t_HO
t_HAA
t _ENDAT
WRITE DATA
t_DDAT
Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. A | Page 31 of 56 | January 2008