ADSP-BF533_15 Datasheet, PDF (31/64 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 16 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
Parameter
Timing Requirements
t_BS BR Asserted to CLKOUT High Setup
t_BH CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
t_SD CLKOUT Low to AMSx, Address, and ARE/AWE Disable
t_SE CLKOUT Low to AMSx, Address, and ARE/AWE Enable
t_DBG CLKOUT High to BG High Setup
t_EBG CLKOUT High to BG Deasserted Hold Time
t_DBH CLKOUT High to BGH High Setup
t_EBH CLKOUT High to BGH Deasserted Hold Time
V_DDEXT = 1.8 V
V_DDEXT = 1.8 V
V_DDEXT = 2.5 V/3.3 V
LQFP/PBGA Packages CSP_BGA Package
All Packages
Min
Max
Min
Max
Min
Max
Unit
4.6
4.6
4.6
ns
1.0
1.0
0.0
ns
4.5
4.5
4.5
ns
4.5
4.5
4.5
ns
6.0
5.5
3.6
ns
6.0
4.6
3.6
ns
6.0
5.5
3.6
ns
6.0
4.6
3.6
ns
CLKOUT
BR
AMSx
ADDR 19-1
ABE1-0
AWE
ARE
BG
BGH
t_BS
t_BH
tSD
tSD
tSD
tDBG
tDBH
tSE
tSE
tSE
t_EBG
t_EBH
Figure 16. External Port Bus Request and Grant Cycle Timing
Rev. I | Page 31 of 64 | August 2013