ADSP-2164_15 Datasheet, PDF (31/39 Pages) Analog Devices – DSP Microcomputers with ROM

ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
BUS REQUEST/BUS GRANT
Parameter
10.24 MHz 13.0 MHz
Min Max Min Max
16.67 MHz Frequency Dependency
Min Max Min
Max
Unit
Timing Requirements:
t_BH BR Hold After CLKOUT High¹ 29.4
t_BS BR Setup Before CLKOUT Low¹ 44.4
Switching Characteristics:
t_SD CLKOUT High to DMS, PMS,
BMS, RD, WR Disable
44.4
t_SDB DMS, PMS, BMS, RD, WR
Disable to BG Low
0
t_SE BG High to DMS, PMS, BMS,
RD, WR Enable
0
t_SEC DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
14.4
24.2
39.2
39.2
0
0
9.2
20.0
0.25t_CK + 5
ns
35.0
0.25t_CK + 20
ns
35.0
0
0
0.25t_CK + 20 ns
ns
0
0
ns
5.0
0.25t_CK – 10
ns
NOTES
1_{If BR meets the tBS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR}
requires a pulsewidth greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual, Third Edition, states that, “When BR is recognized, the processor responds immedi-
ately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after BR is recognized.
No external synchronization circuit is needed when BR is generated as an asynchronous signal.
t_BH
CLKOUT
BR
t_BS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
t_SD
t_SEC
t_SDB
t_SE
Figure 29. Bus Request/Grant
REV. 0
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