AD9877 Datasheet, PDF (31/36 Pages) Analog Devices – Mixed-Signal Front End Set-Top Box, Cable Modem

On the other hand, when the source voltage equals the value
previously stored on CH, the hold capacitor requires no input
current and the equivalent input impedance is extremely high.
Adding series resistance between the output of the signal source
and the AIN pin reduces the drive requirements placed on the
signal source. Figure 41 shows this configuration.
<50Ω
AINP
V_S
SHUNT
<50Ω
AINN
Figure 41. Simple ADC Drive Configuration
The bandwidth of the particular application limits the size of
this resistor. To maintain the performance outlined in the data
sheet specifications, the resistor should be limited to 50 Ω or
less. For applications with signal bandwidths less than 10 MHz,
the user can proportionally increase the size of the series
resistor. Alternatively, adding a shunt capacitance between the
AIN pins can lower the ac load impedance. The value of this
capacitance will depend on the source resistance and the
required signal bandwidth. In systems that must use dc-
coupling, use an op amp to comply with the input requirements
of the AD9877.
OP AMP SELECTION GUIDE
Op amp selection for the AD9877 is highly application
dependent. In general, the performance requirements of any
given application can be characterized by either time domain or
frequency domain constraints. In either case, one should
carefully select an op amp that preserves the performance of the
ADC. This task becomes challenging when one considers the
high performance capabilities of the AD9877 coupled with
other system level requirements, such as power consumption
and cost. The ability to select the optimal op amp can be further
complicated by either limited power supply availability and/or
limited acceptable supplies for a desired op amp.
Newer, high performance op amps typically have input and
output range limitations in accordance with their lower supply
voltages. As a result, some op amps will be more appropriate in
systems where ac coupling is allowed. When dc coupling is
required, op amp headroom constraints (such as rail-to-rail op
amps), or instances where larger supplies can be used, should be
considered.
AD9877
Analog Devices offers differential output operational amplifiers,
such as the AD8131, with a fixed gain of 2. They can be used for
differential or single-ended-to-differential signal conditioning
with 8-bit performance to directly drive ADC inputs. The
AD8138 is a higher performance version of the AD8131. It
provides 12-bit performance and allows different gain settings.
Please contact the local sales office for updates on the latest
Analog Devices amplifier product offerings.
ADC DIFFERENTIAL INPUTS
The AD9877 uses a 1 V p-p input span for the 8-bit ADC inputs
and a 2 V p-p for the 12-bit ADC. Since not all applications
have a signal preconditioned for differential operation, there is
often a need to perform a single-ended-to-differential
conversion. In systems that do not need a dc input, an RF
transformer with a center tap is the best method to generate
differential inputs beyond 20 MHz for the AD9877. This
provides all the benefits of operating the ADC in the differential
mode without contributing additional noise or distortion. An
RF transformer also has the added benefit of providing
electrical isolation between the signal source and the ADC. An
improvement in THD and SFDR performance can be realized
by operating the AD9877 in differential mode. The
performance enhancement between the differential and single-
ended mode is most considerable as the input frequency
approaches and goes beyond the Nyquist frequency (fIN > fS/2).
The AD8131 provides a convenient method of converting a
single-ended signal to a differential signal. This is an ideal
method for generating a signal directly coupled to the AD9877.
The AD8131 will accept a signal swinging below 0 V and shift it
to an externally provided common-mode voltage. The AD8131
configuration is shown in Figure 42.
SINGLE-ENDED
ANALOG INPUT
R1
R2
+
AD8131
R1 –
R2
AD9877
AINP
AINN
Figure 42. Single-Ended-to-Differential Input Drive
Rev. B | Page 31 of 36