AD9864_15 Datasheet, PDF (31/44 Pages) Analog Devices – IF Digitizing Subsystem

AD9864
Σ-∆ ADC
FS
DEC1
÷12
GCP
VGA
DAC
C_DAC
DEC2
AND
DEC3
I+Q
I+Q
AGCR
REF LEVEL
SELECT
LARGER
+
K
1
(1 – Z^–1)
AGCA/AGCD
SCALING
AGCV
SETTING
RSSI DATA
Figure 58. Functional Block Diagram of VGA and AGC
DVGA
I/Q DATA
TO SSI
TO SSI
VARIABLE GAIN CONTROL
The variable gain control is enabled by setting the AGCR field
of Register 0x06 to 0. In this mode, the gain of the VGA (and
the DVGA) can be adjusted by writing to the 16-bit AGCG
register. The maximum update rate of the AGCG register via
the SPI port is fCLK/240. The MSB of this register is the bit that
enables 16 dB of attenuation in the mixer. This feature allows
the AD9864 to cope with large level signals beyond the VGA’s
range (i.e., > –18 dBm at LNA input) to prevent overloading of
the ADC.
The lower 15 bits specify the attenuation in the remainder of
the signal path. If the DVGA is enabled, the attenuation range
is from –12 dB to +12 dB since the DVGA provides 12 dB of
digital gain. In this case, all 15 bits are significant. However,
with the DVGA disabled, the attenuation range extends from
0 dB to 12 dB and only the lower 14 bits are useful. Figure 59
shows the relationship between the amount of attenuation and
the AGC register setting for both cases.
12
ONLY
VGA ENABLED
6
DVGA AND
VGA ENABLED
0
VGA
RANGE
–6
DVGA
RANGE
–12
0000
1FFF
3FFF
5FFF
AGCG SETTING (HEX)
7FFF
Figure 59. AGC Gain Range Characteristics vs. AGCG Register
Setting with and without DVGA Enabled
Referring to Figure 58, the gain of the VGA is set by an 8-bit
control DAC that provides a control signal to the VGA appear-
ing at the gain control pin (GCP). For applications implement-
ing automatic gain control, the DAC’s output resistance can be
reduced by a factor of 9 to decrease the attack time of the AGC
response for faster signal acquisition. An external capacitor,
CDAC, from GCP to analog ground is required to smooth the
DAC’s output each time it updates as well as to filter wideband
noise. Note that CDAC, in combination with the DAC’s pro-
grammable output resistance, sets the –3 dB bandwidth and
time constant associated with this RC network.
A linear estimate of the received signal strength is performed at
the output of the first decimation stage (DEC1) and output of
the DVGA (if enabled), as discussed in the AGC section. This
data is available as a 6-bit RSSI field within an SSI frame with
60 corresponding to a full-scale signal for a given AGC attenua-
tion setting. The RSSI field is updated at fCLK/60 and can be used
with the 8-bit attenuation field (or AGCG attenuation setting)
to determine the absolute signal strength.
The accuracy of the mean RSSI reading (relative to the IF input
power) depends on the input signal’s frequency offset relative
to the IF frequency since both DEC1 filter’s response as well as
the ADC’s signal transfer function attenuate the mixer’s
downconverted signal level centered at fCLK/8. As a result, the
estimated signal strength of input signals falling within prox-
imity to the IF is reported accurately, while those signals at
increasingly higher frequency offsets incur larger measurement
errors. Figure 60 shows the normalized error of the RSSI read-
ing as a function of the frequency offset from the IF frequency.
Note that the significance of this error becomes apparent when
determining the maximum input interferer (or blocker) levels
with the AGC enabled.
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