AD9257 Datasheet, PDF (31/40 Pages) Analog Devices – Octal, 14-Bit, 40/65 MSPS, Serial LVDS

Data Sheet
AD9257
MEMORY MAP REGISTER TABLE
The AD9257 uses a 3-wire interface and 16-bit addressing and,
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Register 0x00, Bit 5 is set high, the
SPI enters a soft reset, where all of the user registers revert to
their default values and Bit 2 is automatically cleared.
Table 17. Memory Map Register Table
Reg.
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Chip Configuration Registers
0x00
SPI port
configuration
0 = SDO LSB first
active
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Soft reset
1=
16-bit
address
1 = 16-bit
address
Soft reset
LSB first
0 = SDO
active
0x01 Chip ID (global)
0x02
Chip grade
(global)
Open
8-bit chip ID, Bits[7:0]
AD9257 0x92 = octal 14-bit, 40 MSPS/65 MSPS serial LVDS
Speed grade ID, Bits[6:4]
001 = 40 MSPS
011 = 65 MSPS
Open
Open
Open
Open
Device Index and Transfer Registers
0x04 Device Index 2
Open
Open
Open
Open
Data
Data
Data
Data
Channel H Channel G Channel F Channel E
0x05 Device Index 1
Open
Open
Clock
Channel
DCO
Clock
Channe
l FCO
Data
Channel D
Data
Channel C
Data
Data
Channel B Channel A
0xFF Transfer
Global ADC Functions
0x08
Power modes
(global)
Open
Open
Open
Open
0x09 Clock (global)
Open
Open
Open
Open Open
Open
Open
Initiate
override
External
power-
down pin
function
0 = full
power-
down
1=
standby
Open
Open
Open
Open
Open
Open
Internal power-down
mode
00 = chip run
01 = full power-down
10 = standby
11 = reset
Open
Open
Duty cycle
stabilize
0 = off
1 = on
Default
Value
(Hex)
0x18
Read
only
0x92
Read
only
0xF
0x3F
0x00
0x00
0x01
Comments
The nibbles
are mirrored
so that LSB
or MSB first
mode registers
correctly. The
default for the
ADCs is 16-bit
mode.
Unique chip ID
that is used to
differentiate
devices; read
only.
Unique
speed grade
ID used to
differentiate
graded
devices.
Read only.
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Set resolution/
sample rate
override.
Determines
various
generic modes
of chip
operation.
Turns duty
cycle stabilizer
on or off.
Rev. 0 | Page 31 of 40