AD73322L Datasheet, PDF (31/40 Pages) Analog Devices – Low Cost, Low Power CMOS General-Purpose Dual Analog Front End

AD73322L
The printed circuit board that houses the AD73322L should be
designed so the analog and digital sections are separated and
confined to certain sections of the board. The AD73322L pin
configuration offers a major advantage in that its analog and
digital interfaces are connected on opposite sides of the package.
This facilitates the use of ground planes that can be easily sepa-
rated, as shown in Figure 38. A minimum etch technique is
generally best for ground planes as it gives the best shielding.
Digital and analog ground planes should be joined in only one
place. If this connection is close to the device, it is recommended
to use a ferrite bead inductor as shown in Figure 38.
DIGITAL GROUND
ANALOG GROUND
Figure 38. Ground Plane Layout
Avoid running digital lines under the device for they will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD73322L to avoid noise coupling. The power
supply lines to the AD73322L should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply lines. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiat-
ing noise to other sections of the board, and clock signals should
never be run near the analog inputs. Traces on opposite sides of
the board should run at right angles to each other. This will
reduce the effects of feedthrough through the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.
Good decoupling is important when using high speed devices.
On the AD73322L both the reference (REFCAP) and supplies
need to be decoupled. It is recommended that the decoupling
capacitors used on both REFCAP and the supplies, be placed as
close as possible to their respective pins to ensure high perfor-
mance from the device. All analog and digital supplies should be
decoupled to AGND and DGND respectively, with 0.1 µF
ceramic capacitors in parallel with 10 µF tantalum capacitors.
In systems where a common supply voltage is used to drive both
the AVDD and DVDD of the AD73322L, it is recommended
that the system’s AVDD supply be used. This supply should
have the recommended analog supply decoupling between the
AVDD pins of the AD73322L and AGND and the recom-
mended digital supply decoupling capacitors between the DVDD
pin and DGND.
DSP PROGRAMMING CONSIDERATIONS
This section discusses some aspects of how the serial port of the
DSP should be configured and the implications of whether Rx
and Tx interrupts should be enabled.
DSP SPORT Configuration
Following are the key settings of the DSP SPORT required for
the successful operation with the AD73322L:
• Configure for External SCLK.
• Serial Word Length = 16 bits.
• Transmit and Receive Frame Syncs required with every word.
• Receive Frame Sync is an input to the DSP.
• Transmit Frame Sync is an:
Input—in Frame Sync Loop-Back Mode
Output—in Nonframe Sync Loop-Back Mode.
• Frame Syncs occur one SCLK cycle before the MSB of the
serial word.
• Frame Syncs are active high.
DSP SPORT Interrupts
If SPORT interrupts are enabled, it is important to note that the
active signals on the frame sync pins do not necessarily corre-
spond with the positions in time of where SPORT interrupts
are generated.
On ADSP-21xx processors, it is necessary to enable SPORT
interrupts and use Interrupt Service Routines (ISRs) to handle
Tx/Rx activity, while on the TMS320CSx processors it is pos-
sible to poll the status of the Rx and Tx registers, which means
that Rx/Tx activity can be monitored using a single ISR that
would ideally be the Tx ISR as the Tx interrupt will typically
occur before the Rx ISR.
DSP SOFTWARE CONSIDERATIONS WHEN
INTERFACING TO THE AD73322L
It is important when choosing the operating mode and hardware
configuration of the AD73322L to be aware of their implica-
tions for DSP software operation. The user has the flexibility
of choosing from either FSLB or NonFSLB when deciding on
DSP to AFE connectivity. There is also a choice to be made
between using autobuffering of input and output samples or
simply choosing to accept them as individual interrupts. As
most modern DSP engines support these modes, this appendix
will attempt to discuss these topics in a generic DSP sense.
Operating Mode
The AD73322L supports two basic operating modes: Frame Sync
Loop Back (FSLB) and NonFSLB (See Interfacing section). As
described previously, FSLB has some limitations when used in
Mixed Mode but is very suitable for use with the autobuffering
feature that is offered on many modern DSPs. Autobuffering
allows the user to specify the number of input or output words
(samples) that are transferred before a specific Tx or Rx SPORT
interrupt is generated. Given that the AD73322L outputs two
sample words per sample period, it is possible using autobuffer-
ing to have the DSP’s SPORT generate a single interrupt on
receipt of the second of the two sample words. Additionally,
both samples could be stored in a data buffer within the data
memory store. This technique has the advantage of reducing the
number of both Tx and Rx SPORT interrupts to a single one at
each sample interval. The user also knows where each sample
is stored. The alternative is to handle a larger number of SPORT
interrupts (twice as many in the case of a single AD73322L)
while also having some status flags to indicate where each new
sample comes from (or is destined for).
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