AD73322 Datasheet, PDF (31/43 Pages) Analog Devices – Low Cost, Low Power CMOS General-Purpose Dual Analog Front End

The AD73322’s ADC inputs are biased about the internal refer-
ence level (REFCAP level), therefore it may be necessary to
bias external signals to this level using the buffered REFOUT
level as the reference. This is applicable in either dc- or ac-
coupled configurations. In the case of dc coupling, the signal
(biased to REFOUT) may be applied directly to the inputs
(using amplifier bypass), as shown in Figure 28, or it may be
conditioned in an external op amp where it can also be biased
to the reference level using the buffered REFOUT signal as
shown in Figure 29 or it is possible to connect inputs directly
to the AD73322’s input op amps as shown in Figure 30.
100pF
50k⍀
50k⍀ VFBN1
VINN1
50k⍀
V_REF
VINP1
50k⍀ _VFBP1
100pF
GAIN
؎1
0/38dB
PGA
V_REF
VOUTP1
VOUTN1
REFOUT
REFCAP
0.1␮F
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
AD73322
Figure 30. Analog Input (DC-Coupled) Using Internal
Amplifiers
In the case of ac coupling, a capacitor is used to couple the
signal to the input of the ADC. The ADC input must be biased
to the internal reference (REFCAP) level which is done by
connecting the input to the REFOUT pin through a 10 kΩ
resistor as shown in Figure 31.
0.1␮F _100⍀
0.047
10k⍀
␮F
VFBN1
VINN1
V_REF
0.1␮F
10k⍀
100⍀
0.047
␮F
VINP1
VFBP1
GAIN
؎1
0/38dB
PGA
V_REF
VOUTP1
VOUTN1
REFOUT
REFCAP
0.1␮F
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
AD73322
AD73322
If the ADC is being connected in single-ended mode, the
AD73322 should be programmed for single-ended mode using
the SEEN and INV bits of CRF and the inputs connected as
shown in Figure 32. When operated in single-ended input
mode, the AD73322 can multiplex one of the two inputs to the
ADC input.
0.1␮F _100⍀
0.047
␮F
10k⍀
VFBN1
VINN1
V_REF
VINP1
VFBP1
GAIN
؎1
0/38dB
PGA
V_REF
VOUTP1
VOUTN1
REFOUT
REFCAP
0.1␮F
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
AD73322
Figure 32. Analog Input (AC-Coupled) Single-Ended
If best performance is required from a single-ended source, it
is possible to configure the AD73322’s input amplifiers as a
single-ended to differential converter as shown in Figure 33.
100pF
50k⍀ VFBN1
50k⍀
VINN1
V_REF
50k⍀
VINP1
50k⍀ VFBP1
100pF
GAIN
؎1
0/38dB
PGA
V_REF
VOUTP1
VOUTN1
REFOUT
REFCAP
0.1␮F
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
REFERENCE
AD73322
Figure 33. Single-Ended to Differential Conversion On
Analog Input
Figure 31. Analog Input (AC-Coupled) Differential
REV. B
–31–