AD5645R_15 Datasheet, PDF (31/36 Pages) Analog Devices – Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference, IC Interface

Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
POWER-ON RESET AND SOFTWARE RESET
The AD56x5R/AD56x5 contain a power-on reset circuit that
controls the output voltage during power-up. The 10-lead
version of the device powers up to 0 V. The 14-lead version has
a power-on reset (POR) pin that allows the output voltage to
be selected. By connecting the POR pin to GND, the AD56x5R/
AD56x5 output powers up to 0 V; by connecting the POR pin to
VDD, the AD56x5R/AD56x5 output powers up to midscale. The
output remains powered up at this level until a valid write sequence
is made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up.
Any events on LDAC or CLR during power-on reset are ignored.
There is also a software reset function. Command 101 is the
software reset command. The software reset command contains
two reset modes that are software programmable by setting bit
DB0 in the input shift register.
Table 16 shows how the state of the bit corresponds to the
software reset modes of operation of the devices. Figure 71
shows the contents of the input shift register during the
software reset mode of operation.
Table 16. Software Reset Modes for the AD56x5R/AD56x5
DB0
Registers Reset to Zero
0
DAC register
Input shift register
1 (Power-On Reset)
DAC register
Input shift register
LDAC register
Power-down register
Internal reference setup register
INTERNAL REFERENCE SETUP (R VERSIONS)
The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
setting DB0 in the input shift register. Table 17 shows how the
state of the bit corresponds to the mode of operation.
Table 17. Reference Setup Command
DB0
Action
0
Internal reference off (default)
1
Internal reference on
X
S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
X
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X RST
COMMAND
DAC ADDRESS
(DON’T CARE)
DON’T CARE
DON’T CARE
Figure 71. Reset Command
R
S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
X
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X REF
COMMAND
DAC ADDRESS
(DON’T CARE)
DON’T CARE
DON’T CARE
Figure 72. Reference Setup Command
Rev. C | Page 31 of 36