ADV7179BCPZ Datasheet, PDF (30/52 Pages) Analog Devices – Chip Scale PAL/NTSC Video Encoder with Advanced Power Management

ADV7174/ADV7179
MODE REGISTER 2 (MR2)
Bits:
Address:
MR27–MR20
SR4–SR0 = 02H
Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can
be read from as well as written to.
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
LOW POWER MODE
MR26
0
1
DISABLE
ENABLE
CHROMINANCE
CONTROL
MR24
0 ENABLE COLOR
1 DISABLE COLOR
GENLOCK CONTROL
MR22 MR21
x 0 DISABLE GENLOCK
0 1 ENABLE SUBCARRIER
RESET PIN
1 1 ENABLE RTC PIN
MR27
RESERVED
BURST
CONTROL
MR25
0 ENABLE BURST
1 DISABLE BURST
ACTIVE VIDEO LINE
DURATION
MR23
0
720 PIXELS
1
710 PIXELS/702 PIXELS
SQUARE PIXEL
CONTROL
MR20
0
DISABLE
1
ENABLE
Figure 40. Mode Register 2
Table 11. MR2 Bit Description
Bit Name
Bit No.
Square Pixel Control
MR20
Genlock Control
MR22–MR21
Active Video Line Duration MR23
Chrominance Control
Burst Control
Low Power Mode
Reserved
MR24
MR25
MR26
MR27
Description
This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a
24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
These bits control the genlock feature of the ADV7174/ ADV7179. Setting MR21 to Logic 1
configures the SCRESET/RTC pin as an input. Setting MR22 to Logic 0 configures the
SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0
following a low-to-high transition on the SCRESET/RTC pin. Setting MR22 to Logic 1 configures
the SCRESET/RTC pin as a real-time control input.
This bit switches between two active video line durations. A 0 selects CCIR REC601 (720 pixels
PAL/NTSC), and a 1 selects ITU-R.BT470 standard for active video duration (710 pixels NTSC
and 702 pixels PAL).
This bit enables the color information to be switched on and off the video output.
This bit enables the burst information to be switched on and off the video output.
This bit enables the lower power mode of the ADV7174/ADV7179. This reduces the DAC
current by 45%.
A Logic 0 must be written to this bit.
Rev. B | Page 30 of 52