ADSP-2115KP-80 Datasheet, PDF (30/64 Pages) Analog Devices – ADSP-2100 Family DSP Microcomputers

ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
CLOCK SIGNALS & RESET
Parameter
13 MHz 13.824 MHz 16.67 MHz
Min Max Min Max Min Max
20 MHz
Min Max
25 MHz
Min Max
Frequency
Dependency
Min
Max Unit
Timing Requirement:
t_CK
CLKIN Period
76.9 150 72.3 150 60 150 50 150 40 150
ns
t_CKL CLKIN Width Low
20
20
20
20
15
20
ns
t_CKH CLKIN Width High
20
20
20
20
15
20
ns
t_RSP
RESET Width Low
384.5
361.5
300
250
200
5t_CK1
ns
Switching Characteristic:
t_CPL CLKOUT Width Low
28.5
26.2
20
15
10
0.5t_CK – 10
ns
t_CPH CLKOUT Width High
28.5
26.2
20
15
10
0.5t_CK – 10
ns
t_CKOH CLKIN High to CLKOUT 0
20 0
20 0
20 0
20 0 15
ns
High
NOTES
1_{Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal}
oscillator startup time).
CLKIN
CLKOUT
t_CK
t_CKH
t_CKL
t_CPL
t_CKOH
t_CPH
Figure 29. Clock Signals
–30–
REV. B