ADSP-21060LCW-160 Datasheet, PDF (30/64 Pages) Analog Devices – SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Synchronous Read/Write—Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
The bus master must meet the bus slave timing requirements.
Table 17. Synchronous Read/Write—Bus Slave
5 V and 3.3 V
Parameter
Min
Max
Unit
Timing Requirements
t_SADRI
Address, SW Setup Before CLKIN
15 + DT/2
ns
t_HADRI
t_SRWLI
t_HRWLI
t_RWHPI
t_SDATWH
Address, SW Hold After CLKIN
RD/WR Low Setup Before CLKIN¹
RD/WR Low Hold After CLKIN²
RD/WR Pulse High
Data Setup Before WR High
5 + DT/2
ns
9.5 + 5DT/16
ns
–4 – 5DT/16
8 + 7DT/16
ns
3
ns
5
ns
t_HDATWH
Data Hold After WR High
1
ns
Switching Characteristics
t_SDDATO
Data Delay After CLKIN³
t_DATTR
Data Disable After CLKIN⁴
t_DACKAD
ACK Delay After Address, SW⁵
t_ACKTR
ACK Disable After CLKIN⁵
18 + 5DT/16
ns
0 – DT/8
7 – DT/8
ns
9
ns
–1 – DT/8
6 – DT/8
ns
1 _{tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min)= 4 + DT/8.}
2 _{For ADSP-21060C specification is –3.5 – 5DT/16 ns min, 8 + 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min, 8 + 7DT/16 ns max.}
3 _{For ADSP-21062/ADSP-21062L/ADSP-21060C specification is 19 + 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max.}
4 _{See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads.}
5 _{tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup times}
greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state
of MMSWS or strobes. A slave will three-state ACK every cycle with t_ACKTR.
CLKIN
ADDRESS
ACK
READ ACCESS
RD
DATA
(OU T)
WRITE ACCESS
WR
t_{S A D R I}
t_DACKAD
t_{S D D A T O}
t_SRWLI
t_{SR W LI}
t_{H ADRI}
t_ACKTR
t_{HRW LI}
t_DATTR
t_{RW HPI}
t_{HRW LI}
t_{RWH PI}
DATA
(IN)
t_SDATWH
Figure 17. Synchronous Read/Write—Bus Slave
t_{H D ATW H}
Rev. H | Page 30 of 64 | March 2013