ADAU1328 Datasheet, PDF (30/32 Pages) Analog Devices – 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec

ADAU1328
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 29 through
Figure 32. Figure 29 shows a typical ADC input filter circuit.
Recommended loop filters for LR clock and master clock as the
PLL reference are shown in Figure 30. Output filters for the
DAC outputs are shown in Figure 31 and Figure 32 for the
noninverting and inverting cases, respectively.
120pF
AUDIO
INPUT
600Z
5.76kΩ
5.76kΩ
100pF
2–
1
OP275
3
+
5.76kΩ
120pF
4.7µF _237Ω
+
1nF
NPO
5.76kΩ
6–
7
OP275
5
+
1nF
NPO
4.7µF _237Ω
+
Figure 29. Typical ADC Input Filter Circuit
ADCxN
100pF
ADCxP
LRCLK
LF
LF
39nF
+
2.2nF
MCLK
5.6nF
390nF
3.32kΩ
562Ω
AVDD2
AVDD2
Figure 30. Recommended Loop Filters for LRCLK or MCLK PLL Reference
240pF
NPO
DAC OUT
4.75kΩ 4.75kΩ
270pF
NPO
3+
1
OP275
2
–
4.99kΩ
4.99kΩ
604Ω ^4.7µF
+
3.3nF
NPO
AUDIO
OUTPUT
49.9kΩ
Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)
DAC
OUT
11kΩ
11kΩ
270pF
NPO
68pF
NPO
3.01kΩ
CM
2–
1 ^{604Ω 4.7µF}
OP275
3
+
+
2.2nF
0.1µF
NPO
AUDIO
OUTPUT
49.9kΩ
Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting)
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