AD9895_15 Datasheet, PDF (30/58 Pages) Analog Devices – CCD Signal Processors with Precision Timing Generator

AD9891/AD9895
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9891/AD9895 AFE signal processing chain is shown in
Figure 36. Each processing step is essential in achieving a high
quality image from the raw CCD pixel data. AFE Register de-
tails are shown in Table XXXI.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc-
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, to be compatible with the 3 V analog
supply of the AD9891/AD9895.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 10 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample
the reference level and the data level, respectively, of the
CCD signal. The placement of the SHP and SHD sampling
edges is determined by the setting of the SHPPOSLOC and
SHDPOSLOC Registers located at Addr 0xE9 and
Addr 0xEA, respectively. Placement of these two clock signals
is critical in achieving the best performance from the CCD.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded
black reference pixels. The AD9891/AD9895 remove this offset
in the input stage to minimize the effect of a gain change on the
system black level. Another advantage of removing this offset at
the input stage is to maximize system headroom. Some area
CCDs have large black level offset voltages, which, if not cor-
rected at the input stage, can significantly reduce the available
headroom in the internal circuitry when higher VGA gain set-
tings are used.
The input clamp is controlled by the CLPDM signal, which is
fully programmable (see Horizontal Clamping and Blanking
section). System timing examples are shown in the Horizontal
Timing Sequence Example section. It is recommended that the
CLPDM pulse be used during valid CCD dark pixels. CLPDM
may be used during the optical black pixels, either together
with CLPOB or separately. The CLPDM pulse should be a
minimum of 4 pixels wide.
PxGA
The PxGA provides separate gain adjustment for the individual color
pixels. A programmable gain amplifier with four separate values,
the PxGA has the capability to “multiplex” its gain value on a
pixel-to-pixel basis (see Figure 37). This allows lower output
color pixels to be gained up to match higher output color pixels.
Also, the PxGA may be used to adjust the colors for white balance,
reducing the amount of digital processing that is needed. The four
different gain values are switched according to the “color
steering” circuitry. Seven different color steering modes for dif-
ferent types of CCD color filter arrays are programmed in the
AD9891/AD9895 AFE CTLMODE Register, at Addr 0x06
(see Figures 39a–39g for internal color steering timing). For
DC RESTORE
1.5V
0.1␮F
CCDIN
SHP
SHD
–2dB TO +10dB
CDS
PxGA
0dB TO 36dB
VGA
REFB
1.0V
1.0␮F
1.0␮F
REFT
2.0V
INTERNAL
V_REF
2V FULL
SCALE
ADC
DOUT
PHASE
10
or
OUTPUT
12
DATA
LATCH
DOUT
0.1␮F
BYP1
0.1␮F _BYP2
0.1␮F
BYP3
CLPDM
INPUT OFFSET
CLAMP
10
VGA GAIN
REGISTER
8-BIT
DAC
OPTICAL BLACK
CLAMP
DIGITAL
FILTER
CLPOB PBLK
8
DOUT
SHP SHD PHASE CLPDM CLPOB PBLK
CLAMP LEVEL
REGISTER
PRECISION
TIMING
GENERATION
V-H
TIMING
GENERATION
Figure 36. AFE Block Diagram
–30–
REV. A