SBCD1756_15 Datasheet, PDF (3/4 Pages) Analog Devices – BCD OUTPUT SYNCHRO TO DIGITAL CONVERTERS

ApplyintgheSBCD1752/1753/1756/1757
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I-- WIDTH DEPENDS ON
I OPTIONISH SPECJ
_I ^I
r--DI~i.tCE DEPENDS
I ,r--OOno VElOCITY ~
~ t-- «IOno
I
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--I I- ^{WIDTH DEPENDS}
ON OPTION
NOT TO SCALE
BUSY
n
RECOMMENDED
J LDATA TRANSFER
TIME IHIOH STATE I
Data Transfer Diagram
The digital output connections in the case of the SBCDI753
and SBCDI757 should be taken from the pins marked "0.1"
through to "200"; these values being represented in degrees.
In the case of the SBCDI752 and SBCDI756, the data should
be taken from the pins marked "0.1" through to "100", these
values also being represented in degrees. In the case of these
latter units the "SIGN" pin will indicate the polarity of the
output, Logic "0" representing positive angles and Logic "I"
representing negative angles.
In the case of a synchro, the signals are connected to S 1, S2
and S3 according to the following convention:
The function of the INHIBIT pin is to enable the user to
Synchro connection
inh,bit the update of the converter's output counter. This is
Esl - 53 = ERLO - RHI Sin wt Sin 8
achieved by taking the INHIBIT pin to a TTL Logic zero. If
Es3 - 52 = ERLO - RHI Sin wt Sin (8 + 1200)
used, the INHIBIT should be applied 400ns after the trailing
edge of the BUSY pulse. This will ensure that the data on the
output pins is valid. The data should then be transferred and
the INHIBIT released before the next BUSY pulse occurs.
The worst case times allowable for data transfer in this case
are shown in the Specifications under the heading of "MAX
O^{DATA TRANSFER TIME (from 400ns After Trailing Edge of}
BUSY at Max Velocity)". It should be noted that the applica-
B _{tion of the INHlBlTwill not prevent the BUSY pulses appear-}
ing on the BUSY pin, and thus if the INHIBIT is not released
S _{by the time that the next BUSY pulse occurs, the BUSY pulse}
O will still appear, although the internal converter loop will have
been opened. Under this condition, a worst case recovery time,
L _{equivalent to that of a step of 179 degrees may be encountered}
r _E 1 _{(see Spec.). To avoid this and to ensure valid data transfer, the}
T^f. _E ^{system shown in the diagram is recommended.}
Es2 - 51 = ERLO - RHI Sin wt Sin (8 + 2400)
For a resolver, the signals are connected to "S I", "S2", "S3"
and "S4" according to the following convention:
Resolver Connection
Esl - 53 = ERLO- RHISin wt Sin 8
Es2 - 54 = ERHI - RLO Sin wt Cos 8
The BUSY and INHIBIT pin (if used), should be connected
as described under the heading "DATA TRANSFER".
The reference connections are made to pins RHI and RLO'
PIN CONNECTION DIAGRAM
Dimensions shown in inches and (mm).
2.625 166,11
3 STATE
ENABLE
<
74113
TRI STATE
LATCHES
PINS 0.040 '0.001 110.16 '0.031 DIA
BRASS HARD GeLD PLATED
141
02115.31
--,--.
SEE
+-NOTE
ICI
11'+
54
......
53
S2
SI
+--+-+
BUSY
0,1
0.2
.....
0.<
0.8
3.125 179.<1
II
TO COMPUTER INPUT PORT
INHIBIT
Suggested External Interface Circuitry
In cases where the converter is connected to a data bus or used
as a peripheral, the method outlined in the above diagram is
recommended. The INHIBIT is not necessary in this case, and
the external "Enable" has control of the converter output.
The AC1755 mounting card described later in this data sheet
contains the external components shown in the diagram.
CONNECTING THE CONVERTER
The power lines, which should not be reversed, should be con-
nected to "+15V", "-15V" and "+5V" in the case of the
SBCD1752 and SBCDI753, and to "+15V" and "+5V" in the
case of the SBCDI756 and SBCDI757, with the common con-
nection to "GND" in all cases.
It is suggested that O.lJlF and 6.8JlF capacitors be placed in
+15V
aNY
~-;-
~
L
0,2616.61
t
RLo
RHo
TOPVIEW
MATING
SEE -
NOTE
IAI
10
20
40
BO
SEE
'001
NOTE~:
~ IBI "t ^.
--11--0RIDOI12.51
SOCKET: CAMBION
NOTES
IAI NOT PRESENT ON
SBCD1156 AND
SBCD115]
IBI ON SBCD1152 AND
SBCD1156MARKED
AS SIGN
ICI PRESENT ON RE,
SOLVER TO 0101.
TAL CONVERTER
IRBCDI ONL y,
450-3388-01-03
RESISTIVE SCALING OF INPUTS
A unique feature of the SBCD17521175 3/1756/1757 con-
verters is tha't the inputs can be resistively scaled to accommo-
date any value of input signal and reference voltage.
In order to calculate the values of the external scaling resistors
necessary, add 1.11 kS1 in series with the inpu t per extra volt
in the case of the signal, and 2.2kS1 per extra volt in the case
of the reference.
parallel from +15V to GND, from -15V to GND and from
+5V to GND.
For example, assume that it is required to use a standard 11.8V
line to line signal, 26V reference converter with 60V line to
line signal and a 115V reference. The resistors should be ar-
ranged as in the diagram.
SYNCHRO & RESOL VER CONVERTERS VOL. /I, 13-43
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