EVAL-AD7891-1CB Datasheet, PDF (3/12 Pages) Analog Devices – Evaluation Board for Single Supply, 12-Bit 454 kSPS ADC

EVAL-AD7891-1CB
SET-UP CONDITIONS
Care should be taken before applying power and signals to the
evaluation board to ensure that all link positions are as per the
required operating mode. Table I shows the position in which
all the links are set when the evaluation board is sent out.
Table I. Initial Link and Switch Positions
1
32
A
B
C
1
32
Figure 1. Pin Configuration for the 96-Way
Connector, J1
Link No. Position Function.
LK1
A Input to buffer 1 comes from V_IN1 SMB
connector.
LK2 - LK8
B Inputs to buffers 2 to 8 connected to
AGND.
LK9 - LK16
A V_INXA inputs are connected to relevant
AINx buffers
LK17 - LK24 C V_INXB inputs are connected to AGND
LK25
B Connects the AD780's V_OUT pin to the
AD7891-1's REF OUT/REF IN pin
and thus selects the AD780 as the
reference source for the AD7891-1
LK26
B V_DD is supplied from the 96-way
connector.
LK27
B +12 V is supplied from the 96-way
connector.
LK28
B -12 V is supplied from the 96-way
connector.
LK29
A STANDBY pin is connected to V_DD and
AD7891-1 does not go into STANDBY
mode.
LK30
B Connects the AD7891-1's CONVST
pin to the FL0 pin of the edge
connector.
LK31
B MODE pin is connected to VDD and
part is configured for its parallel
operating mode.
EVALUATION BOARD INTERFACING
Interfacing to the evaluation board is either via a 96-way
connector, J1 or a 9-way D-Type connector, J2. J1 is used to
connect the evaluation board to the EVAL-CONTROL
BOARD. It can also be used for parallel interface connections to
the evaluation board when operating the AD7891 in its parallel
interface mode without the EVAL-CONTROL BOARD. J2 is
used for serial interface connections when operating the
AD7891 in its serial interface mode. The pinout for the J1
connector is shown in Figure 1 and its pin designations are
given in Table II. The pinout for the J2 connector is given in
Figure 2 and its corresponding pin designations are given in
Table III.
96-Way Connector Pin Description
D0-D11
Data Bit 0 to Data Bit 11. These are three-
state TTL-compatible outputs from the
AD7891-1. Parallel data from the part is
obtained at these pins.
DGND
Digital Ground. These lines are connected to
the digital ground plane on the evaluation
board. It allows the user to provide the digital
supply via the connector along with the other
digital signals.
RD
Read. This is an active low logic input which
is used in conjunction with CS low to enable
the data outputs.
CS
Chip Select. This is an active low logic input
which is used in conjunction with RD low to
enable the data outputs and with WR to allow
input data to be written to the part.
WR
Write Input. This is an active low logic input
used in conjunction with CS to latch the
multiplexer address and software control
information.
FL0
Flag zero. This is a logic input and is con-
nected to the CONVST logic input on the
device via LK17. A low to high transition on
this input puts the track/hold amplifier into its
hold mode and starts a conversion.
IRQ2
Interrupt Request 2. This is a logic output
and is directly connected to the EOC logic
output on the device. This active low logic
output indicates the converter status. The end
of conversion is signified by a low-going pulse
on this line.
AGND
Analog Ground. These lines are connected to
the analog ground plane on the evaluation
board.
AV_DD
+12 V
Analog +5V Supply. These lines are con-
nected to the V_DD supply line on the board.
+12 V supply used to power op-amps and
voltage reference.
-12 V
-12 V supply used to power op-amps.
REV. A
–3–