DRC1746_15 Datasheet, PDF (3/8 Pages) Analog Devices – HIGH POWER OUTPUT HYBRID DIGITAL TO SYNCHRO RESOLVER CONVERTERS

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Page 12
DRC1745/DRC1746
THEORY OF OPERATION
The operation of the DRCI745 and DRCI746 is illustrated in
the block diagram shown in Figure I.
The reference voltage, VR,EF,(A sin wt) is multiplied by both
Sin a and Cos e where 6 is the digital angle. The resultant outputs
then pass through the current booster output stage to provide
the resolver format output voltages viz:
2A Sinwt Sin e
and 2ASinwtCos6
(Sine output)
(Cosoutput)
(Note: Convener has a gain of 2 from input to output.)
+ 1511 -'1;11
+'SII(P!
The sine and cosine outputs are taken from the "Sin" and "Cos"
pins with "81G GND" as the common connection.
The remote sense facility using "Cos Sense" and "Sin Sense"
connections should be used as described under the "Remote
Output Sensing" heading, If not used, the sense OUtputs should
be connected to the corresponding Sin and Cos outputs.
DIGITAL DATA INPUT
The digital input to the converters is internally buffered by
transparent latches. The latches will be CMOS (type 54C373)
or low power Schottky (LSXtype 54LS373) depending on the
option.
SIN SENSE
The "HBE" input controls the input of the most significant 8
bits and the "LBE" input controls the input of the least significant
OBSOLEXXXJ Tr><>E<><:><: A...
'A ;;~'wt! Au>
+511
'L OPTIONS
ONLY!
SIN
(2A SIN ",' SIN III
SIG GNO
COS SENSE
COs
(2.0 SIN .,t COS '"
LBE HUE
DIGITAL
IN_,P_IU_, T
"ND.- 15111PI
NOTE, ".0'0'" "GNO.', AND " ""'D" ARE INTERHALLYCONNECTED
IN STAR POINT.
Figure 7. Theory of Operation
bits (6 in the case of the DRCI745 and 8 in the case of the
DRC1746).
A logic "Hi" on the control lines causes the input to appear
transparent and the converter output will follow the changes on
the digital input. When "HBE" and "LBE" arc taken to a logic
"Lo" state, the converter output will be latched at the level of
the data present on the inpUt at the low going edge and remains
constant until "HBE" and "LBE" arc taken to a "Hi" state
again. If the latches are not required, "HBE" and "LBE" can
be left open circuit. The timing diagram in Figure 2 illustrates
the use of "HBE" and "LBE".
Internal resistive pull-ups (to + 5V using 27k resistors) are
employed on all digital inputs. This ensures full TTL compatibility
for either latch option even when sourcing 50j.1Aof leakage
current into each external digital driver.
D',~~
I STA8lE DATA
CONNECTING THE CONVERTER
The connections to the DRCl745 and DRC1746 are very
straightforward.
H8,"l8E
n^I
I
I
I
I
I
,
II
i
The digital inputs should be connected to the converter using
~_{, I}
t,
It,. 5n,MAXLSOPTiONS
I
140nsMAXCMOSOPTiONS
, t, "20n.MAXLSOPTIONS
pins 1 (MSB) through 14 (LSB) in the case of the DRCl745
I
,
On,MAXCMOSOPTIONS
and through 16 (LSB) in the case of the DRCI746. The format
of the digital angular input is shown under the "Bit Weight
NOTE, INTERNAUATCHES ARE, S313(LS! S4CJ1JICMOSt
Table" section on this page.
Figure 2. Data Transfer Diagram
The digital input control lines should be connected as described
under the "Digital Data Input" section.
BIT WEIGHT TABLE
ALOand Am are for the analog input reference voltage (VREF).
It should be noted that this is a single ended input where ALo is
grounded internally. If it is desired, the VIlEF input can be
externally isolated using the STMI680 or STMI660 transformer.
See the section on "Output and Reference Transformers".
The converters have separate power supply inputs for the output
amplifier stage ( + 15V(P) and - 15V(P» and for the remainder
of the converter (+ 15V and -15V), When dc power supplies
arc used for the output stage, the supplies may'be linked. However,
when pulsating power supplies are used for the output stage, a
separate dc supply must be provided for the + 15V and -15V
Bit Number
1 (MSB)
2
3
4
5
6
7
8
9
10
Wdght inDepees
180.0000
90.0000
45.0000
22.5000
11.2500
5,6250
2,8125
1.4063
Qro31
0.3516
requirement, The conveners have internal capacitive decoupling
of 47nF on both power stage and convener supply but it is
recommended that 6.8~F capacitors arc taken from the + 15V
and -15V pin to "GND",
The "Case" pin is joined to the case which is isolated and should
be: WlUlect~ to a convenient zero potential point in the system.
II
12
13
14 (LSBDRCI745)
15
16 (LSBDRCI746)
Ql~8
0.0879
0.0439
0.0220
0.0110
0.0055
REV,A
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