DAS1158_15 Datasheet, PDF (3/4 Pages) Analog Devices – LowPower14-B-it,15Bit& 16-Bit SamplingAnalog-to-DigitaClonverters

- ANALOGDEVICES FAX-ON-DEMANDHOTLINE
Page B
[
Applyingthe DAS1157/DAS1158/DAS1159
OPERATION
Errors due to source loading are eliminated since the samplClhold
For operation, the only connections necessary to the DASl1S71 ^{amplifier is a high-impedance unity-gain amplifier. High feed-}
DASllS8IDASllS9 are the :t:15V and + SV power supplies,
through rejection is provided for either single-channc1or multi.
analog input signal, trigger pulse, and the HI-ENABLElLO-
channel applications. Feedthrough rejection can be optimized,
ENABLE tn-state controls. Analog input and digital. output
in multiclwmc1 applications, by changing channels at the rising
p~
are user selectable via external jumper
or falling edge of the 8tH control pulse.
connections.
TIMING D IAGRAM
Input voltaiC ranges arc selectable via user pin programming: 0
to +5V,Oto +lOV, :t:SVand :t:lOV. Unipolar coding is provided
in trUe binary format with bipolar coding displayed in offset
binary and tWo'Scomplement (DASI lS7and DAS1l58). DAS1159
unipolar coding is provided in a modified binary format (MSB
The timing diagram for the DASIlS7/DA51l58/DA81159 is
illustrated in Figure 3. This figure also includes the samplClhold
amplifier acquisition time.
If the samplelhold amplifier is required, the TRIGGER input
complement) while bipolar coding is tWo's complement only.
and 5tH CONTROL terminal can be tied together providing
only one conversion control signal. When the trigger pulse goes
ANALOG INPUT SECTION
high, it places the samplelbold amplifier in the sample mode
The analog input can be applied to just the AID converter or to
allowing it to acquire the present input signal. The trigger pulse
OBSOLETE I the internal samplelhold ampliflCt"ahead of the AID converter.
When using just the AID converter, apply the analog input per
the voltap: ranae pin programming shown in Table I. When
using the samplelhold amplifier in conjunction with AID con-
verter, apply the analog input to the SIH INPUT terminal and
connect the SIH OUTPUT terminal to the appropriate AID
converter analog input.
Ana1o&Voitap
laplat
IWIJe
010 + SV
Coan.ct
V1Nor S/H Out
To
ANA IN I,
ANA IN 2,
ANA IN 3
Connect
AnaJos Common
To
CoaDect
ltefOuI
To
Ground
NC"
010 + IOV
ANA IN 2
ANAIN3
Ground
NC"
ANA IN J
5V
ANA IN 1
Ground,
ANAIN2
ANAIN3
must remain high for a minimum of 5..,.sto insure accuracy. If
the samplelhold amplifier is not used, the trigger pulse needs to
be Iv-s (minimum) in length to satisfy the AID converter trigger
requirements. At the fa1.Linegdge of the trigger pulse, the sample!
hold amplifier is placed in the hold mode, all internal logic is
reset and the AID conversion begins. The conversion process
can be retriggc:red at any time, including duno, conversion.
With this negative edge of the trigger pulse, the MSB is set
high with the I"f'mainingdigital.outputs set to logic low state,
and the end of conversion is set high and remains high through
the full conversion cycle. During conversion each bit, starting
with the MSB, is sequentially switched high at the rising edge
of the internal clock. The DAC output is then compared to the
analog input and the bit decision is made. Each comparison
lasts onc clock cycle with the complete 14-/15./16-bit conversion
taking SOIoUmlaximum. At this time, the end of conversion line
goes low signjfying that the conversion is complete. For micro-
processor bus applications, the digital output can now be applied
lOV
ANAIN3
Ground,
ANA IN 2 to the data bus by enabling the tri-state buffers. For muimum
ANA IN 1
data throughpUt, the digital output data should be read while
'NOCOlUlCC:lion
the samplelhold amplifier is acquiring the new analog input
Table I. Analog Input Pin Programming
signal.
REf OUT
,,
,
I CONNECT
:^{I fOR}
I IJPOLAII
, ^{0fI£IIATION}
ANAIH1
I_{L- ---- ANAIN Z}
,..,IN S
SII4 OUTPUT
SlH IHI'UT
SII4 CONTfIOl
GAIN
ADJUST
'4-111-111-
BIT
AIO
CONVEInaI
,
.n ^TAlGGfRi
SII4 COHTROl
,,
INl'UT +fS
E^{- -r SIGNAL}
-F⁰S
+fS
-,'
I
~- SIH OUTP\JT_-FS0 _-, : ,
roc---1--50... .!1x----
NOns
'AI 1. Output o.ta V.Iid.
0 Z. IfSlHContra' .nd Tri11'IIM'" . -n.d T--.
PuIM_1ft Mutt lie 5... Min'0 Allow,to.
SIH~
to Acquln _In, Sign". If
tll. ADCia Only UMd. 1ft. Trig"" PuIM_t
lie 1". MIn.
Figure 2. Analog Input Block Diagram
Figure 3. DAS 1157/DAS 1158/DAS 1159 Timing Diagram
.J