ADV473 Datasheet, PDF (3/12 Pages) Analog Devices – CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC

ADV473
TIMING CHARACTERISTICS¹
(V_AA2 = 5 V; V_REF = 1.235 V; R_L = 37.5 Ω, C_L = 10 pF; R_SET = 140 Ω.
All specifications T_MIN to T_MAX3 unless otherwise noted.)
Parameter
135 MHz
Version
110 MHz
Version
80 MHz
Version
66 MHz
Version
Units
Conditions/Comments
fmax
t₁
t₂
t₃₄
t₄₄
t₅₅
t₆₅
t₇
t₈
t₉
t₁₀
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
t₁₇
t₁₈
t₁₉₆
t_SK
t_PD
135
10
10
3
40
20
5
10
10
100
50
40
2
2
7.4
3
2
30
3
13
2
4 × t₁₄
110
10
10
3
40
20
5
10
10
100
50
40
3
3
9.1
3.5
3
30
3
13
2
4 × t₁₄
80
10
10
3
40
20
5
10
10
100
50
40
3
3
12.5
4
4
30
3
13
2
4 × t₁₄
66
10
10
3
40
20
5
10
10
100
50
40
3
3
15.15
5
5
30
3
13
2
4 × t₁₄
MHz
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns max
ns max
ns
Clock Rate
RS0–RS2 Setup Time
RS0–RS2 Hold Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus 3-Stated
Read Data Hold Time
Write Data Setup Time
Write Data Hold Time
CR0–CR3 Delay Time
RD, WR Pulse Width Low
RD, WR Pulse Width High
Pixel & Control Setup Time
Pixel & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay
NOTES
1_{TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and}
outputs. Analog output load ≤ 10 pF, D0-D7 output load ≤ 50 pF. See timing notes in Figure 2.
2_{VAA = 5 V ± 5%.}
3_{Temperature range (TMIN to TMAX); 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C .}
4_{t3 and t4 are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V.}
5_{t5 and t6 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is}
then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the times, t ₅ and t₆, quoted in the timing characteristics are the
true values for the device and, as such, are independent of external bus loading capacitances.
6_{Settling time does not include clock and data feedthrough.}
Specifications subject to change without notice.
RS0, RS1,
RS2
RD, WR
D0–D7
(READ)
D0–D7
(WRITE)
t₁
t₂
VALID
t₄
t₃
CR0–CR3
t₁₀
t₁₁
t₅
DATA OUT (RD = 0)
t₆
DATA IN (WR = 0)
t₇
t₈
t₉
Figure 1. MPU Read/Write Timing
t₁₄
t₁₅ t₁₆
CLOCK
R0-R7, G0–G7,
B0–B7,
DATA
OL0-OL3, S0–S1,
SYNC, BLANK
IOR, IOG, IOB
t₁₂
t₁₇
t₁₉
t₁₃
t₁₈
NOTES
1. OUTPUT DELAY MEASURED FROM THE 50% POINT OF THE RISING EDGE
OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. SETTLING TIME MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO THE OUTPUT REMAINING WITHIN ±1 LSB.
3. OUTPUT RISE/FALL TIME MEASURED BETWEEN THE 10% AND 90%
POINTS OF FULL-SCALE TRANSITION.
TO
OUTPUT
PIN
50pF
3.2mA
+2.1V
400µA
Figure 2. Video Input/Output Timing
Figure 3. Load Circuit for Bus
Access and Relinquish Time
REV. A
–3–