ADF4217L Datasheet, PDF (3/24 Pages) Analog Devices – Dual Low Power Frequency Synthesizers

ADF4217L/ADF4218L/ADF4219L
Parameter
NOISE CHARACTERISTICS⁶
RF Phase Noise Floor⁷
IF Phase Noise Floor⁷
Phase Noise Performance⁸
RF⁹
RF¹⁰
IF¹¹
IF¹²
Spurious Signals
RF⁹
RF¹⁰
IF¹¹
IF¹²
BChips²
B Version¹ (Typical)
Unit
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
1.95 GHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
900 MHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
Measured at Offset of f_PFD/2f_PFD
NOTES
1_{Operating temperature range is as follows: B Version: –40°C to +85°C.}
2_{The BChip specifications are given as typical values.}
3_{This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency}
that is less than this value.
4_{Guaranteed by design. Sample tested to ensure compliance.}
5_{This includes relevant IP.}
6_{VDD = 3 V; P = 16/32; IFIN /RFIN for ADF4218L, ADF4219L = 540 MHz/900 MHz.}
7_{The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).}
8_{The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN}
for the synthesizer. (f_REFOUT = 10 MHz @ 0 dBm.)
9_{fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fRF = 1.95 GHz; N = 65000; Loop B/W = 3 kHz}
10_{fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz}
11_{fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 30000; Loop B/W = 3 kHz}
12_{fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 4500; Loop B/W = 20 kHz}
Specifications subject to change without notice.
TIMING CHARACTERISTICS (V_DD1 = V_DD2 = 3 V ؎ 10%, 5 V ؎ 10%; V_DD1, V_DD2 ≤ V_P1,
V_P2 ≤ 6.0 V ; AGND_RF1 = DGND_RF1 = AGND_RF2 = DGND_RF2 = 0 V; T_A = T_MIN to T_MAX, unless otherwise noted.)
Parameter
Limit at
T_MIN to T_MAX
(B Version)
t₁
10
t₂
10
t₃
25
t₄
25
t₅
10
t₆
50
Guaranteed by design but not production tested.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
REV. C
CLOCK
DATA DB21 (MSB)
LE
LE
t₁
t₂
DB20
t₃
t₄
DB2
DB1
(CONTROL BIT C2)
Figure 1. Timing Diagram
–3–
DB0 (LSB)
(CONTROL BIT C1)
t₆
t₅