ADF4210 Datasheet, PDF (3/20 Pages) Analog Devices – Dual RF/IF PLL Frequency Synthesizers

ADF4210/ADF4211/ADF4212/ADF4213
Parameter
B Version B Chips² Unit
Test Conditions/Comments
POWER SUPPLIES
V_DD1
V_DD2
V_P
I_DD (RF + IF)⁶
ADF4210
ADF4211
ADF4212
ADF4213
I_DD (RF Only)
ADF4210
ADF4211
ADF4212
ADF4213
I_DD (IF Only)
ADF4210
ADF4211
ADF4212
ADF4213
I_P (I_P1 + I_P2)
Low-Power Sleep Mode
2.7/5.5
V_DD1
V_DD1/6.0
11.5
15.0
17.5
20
6.75
10
12.5
15
5.5
5.5
5.5
5.5
1.0
1
2.7/5.5
V_DD1
V_DD1/6.0
V min/V max
V min/V max V_DD1, V_DD2 Յ V_DD1, V_DD2 Յ 6.0 V
11.5
mA max
9.0 mA typical
15.0
mA max
11.0 mA typical
17.5
mA max
13.0 mA typical
20
mA max
15 mA typical
6.75
mA max
5.0 mA typical
10
mA max
7.0 mA typical
12.5
mA max
9.0 mA typical
15
mA max
11 mA typical
5.5
mA max
4.5 mA typical
5.5
mA max
4.5 mA typical
5.5
mA max
4.5 mA typical
5.5
mA max
4.5 mA typical
1.0
mA max
T_A = 25°C, 0.55 mA typical
1
µA typ
NOISE CHARACTERISTICS
ADF4213 Phase Noise Floor⁷
Phase Noise Performance⁸
ADF4210/ADF4211, IF: 540 MHz Output⁹
ADF4212/ADF4213, IF: 900 MHz Output¹⁰
ADF4210/ADF4211, RF: 900 MHz Output¹⁰
ADF4212/ADF4213, RF: 900 MHz Output¹⁰
ADF4211/ADF4212, RF: 1750 MHz Output¹²
ADF4211/ADF4212, RF: 1750 MHz Output¹³
ADF4212/ADF4213, RF: 2400 MHz Output¹⁴
Spurious Signals
ADF4210/ADF4211, IF: 540 MHz Output⁹
ADF4212/ADF4213, IF: 900 MHz Output¹⁰
ADF4210/ADF4211, RF: 900 MHz Output¹⁰
ADF4212/ADF4213, RF: 900 MHz Output¹⁰
ADF4211/ADF4212, RF: 1750 MHz Output¹²
ADF4211/ADF4212, RF: 1750 MHz Output¹³
ADF4212/ADF4213, RF: 2400 MHz Output¹⁴
–171
–164
–91
–89
–89
–91
–85
–67
–88
–88/–90
–90/–94
–90/–94
–90/–94
–80/–82
–65/–70
–80/–82
–171
–164
–91
–89
–89
–91
–85
–67
–88
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
See Note 11
See Note 11
See Note 11
See Note 11
@ 200 Hz Offset and 10 kHz PFD Frequency
@ 1 kHz Offset and 1 MHz PFD Frequency
–88/–90
–90/–94
–90/–94
–90/–94
–80/–82
–65/–70
–80/–82
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
See Note 11
See Note 11
See Note 11
See Note 11
@ 10 kHz/20 kHz and 10 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1_{Operating temperature range is as follows: B Version: –40°C to +85°C.}
2_{The B Chip specifications are given as typical values.}
3_{This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is}
less than this value.
4_{VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels, TA = 25°C.}
5_{Guaranteed by design. Sample tested to ensure compliance.}
6_{VDD = 3 V; P = 16; RFIN = 900 MHz; IFIN = 540 MHz, TA = 25°C.}
7_{The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See}
TPC 16.
8_{The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the}
REFIN for the synthesizer (f_REFOUT = 10 MHz @ 0 dBm).
9_{fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz.}
10_{fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.}
11_{Same conditions as listed in Note 10.}
12_{fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.}
13_{fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.}
14_{fREFIN = 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.}
Specifications subject to change without notice.
REV. A
–3–