ADCLK846 Datasheet, PDF (3/16 Pages) Analog Devices – 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

ADCLK846
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for VS = 1.8 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full
VS = 1.8 V ± 5% and TA = −40°C to +85°C variations, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted.
Table 1.
Parameter
Symbol Min
Typ Max
Unit Conditions
CLOCK INPUTS
Differential input
Input Frequency
0
1200
MHz
Input Sensitivity, Differential
150
mV p-p Jitter performance is improved with higher slew
rates (greater voltage swing)
Input Level
1.8
V p-p Larger voltage swings can turn on the protection
diodes and can degrade jitter performance
Input Common-Mode Voltage VCM
Input Common-Mode Range VCMR
VS/2 − 0.1
0.4
VS/2 + 0.05 V
VS − 0.4
V
Inputs are self-biased; enables ac coupling
Inputs are dc-coupled with 200 mV p-p signal
applied
Input Voltage Offset
30
mV
Input Sensitivity, Single-Ended
150
mV p-p CLK ac-coupled; CLK ac-bypassed to ground
Input Resistance (Differential)
7
kΩ
Input Capacitance
CIN
Input Bias Current (Each Pin)
−350
2
+350
pF
μA
Full input swing
LVDS CLOCK OUTPUTS
Output Frequency
Differential Output Voltage
Offset Voltage
Short-Circuit Current
VOD
ΔVOD
VOS
ΔVOS
ISA, ISB
247
1.125
1200
344 454
50
1.25 1.375
50
36
Termination = 100 Ω; differential (OUTx, OUTx)
MHz See Figure 9 for a swing vs. frequency plot
mV
mV
V
mV
mA
Each pin (output shorted to GND )
CMOS CLOCK OUTPUTS
Output Frequency
Output Voltage High
Output Voltage Low
Reference Voltage
Output Voltage
Output Resistance
Output Current
Single-ended; termination = open
OUTx and OUTx in phase
250
MHz With 10 pF load each output; see Figure 16 for
swing vs. frequency
VOH
VS − 0.1
V
At 1 mA load
VS − 0.35
VOL
V
At 10 mA load
0.1
V
At 1 mA load
0.35
V
At 10 mA load
VREF
VS/2 − 0.1 VS/2 VS/2 + 0.1 V
60
Ω
±500 μA
500
μA
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