AD9070_15 Datasheet, PDF (3/16 Pages) Analog Devices – 10-Bit, 100 MSPS A/D Converter

AD9070
Parameter
Test
AD9070BR
Temp Level Min Typ Max
5962-9756301HXC
Min Typ
Max
Unit
DYNAMIC PERFORMANCE⁵
Transient Response
25°C V
3
3
ns
Overvoltage Recovery Time
25°C V
4
4
ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f_IN = 10.3 MHz
25°C I
55 57
55 57
dB
Full
V
56
55
dB
f_IN = 41 MHz
25°C I
54 56
54 56
dB
Full
V
55
54
dB
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
f_IN = 10.3 MHz
25°C I
54 56
54 56
dB
Full
V
55
54
dB
f_IN = 41 MHz
25°C I
51 54
51 54
dB
Full
V
53
52
dB
Effective Number of Bit
f_IN = 10.3 MHz
25°C I
8.8 9.2
8.8 9.2
Bits
f_IN = 41 MHz
25°C I
8.3 8.9
8.3 8.9
Bits
2nd Harmonic Distortion
f_IN = 10.3 MHz
25°C I
63 70
63 70
dBc
f_IN = 41 MHz
25°C I
58 63
58 63
dBc
3rd Harmonic Distortion
f_IN = 10.3 MHz
25°C I
65 71
65 71
dBc
f_IN = 41 MHz
25°C I
57 61
57 61
dBc
Two-Tone Intermod Distortion (IMD)
f_IN = 10.3 MHz
f_IN = 41 MHz
25°C V
70
25°C V
60
70
dBc
60
dBc
NOTES
1_{Gain error and gain temperature coefficient are based on the ADC only (with a fixed –2.5 V external reference).}
2_{tV and tPD are measured from the threshold crossing of the ENCODE input to the 50% levels of the digital outputs. The output ac load during test is 10 pF.}
3_{Power dissipation is measured under the following conditions: fS 100 MSPS, analog input is –1 dBFS at 10.3 MHz. Power dissipation does not include the current of}
the external ECL pull-down resistors that set the current in the ECL output followers.
4_{A change in input offset voltage with respect to a change in VEE.}
5_{SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range.}
Typical thermal impedance for the R style (SOIC) 28-lead package: θ_JC = 23°C/W, θ_CA = 48°C/W, θ_JA = 71°C/W.
Typical thermal impedance for the DH style (Ceramic DIP) 28-lead package: θ_JC = 8°C/W, θ_CA = 43°C/W, θ_JA = 51°C/W.
Contact DSCC to obtain the latest revision of the 5962-9756301 drawing.
Specifications subject to change without notice.
SAMPLE N–1 SAMPLE N
SAMPLE N+3
SAMPLE N+4
AIN
ENCODE
ENCODE
D9–D0
t_A
t_EH
SAMPLE N+1
t_EL
1/fs
SAMPLE N+2
DATA N–4
DATA N–3
DATA N–2
t_PD
DATA N–1
DATA N
t_V
DATA N+1
Figure 1. Timing Diagram
REV. C
–3–