AD8193_15 Datasheet, PDF (3/16 Pages) Analog Devices – Buffered 2:1 TMDS Switch

AD8193
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2⁷ − 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Bit Error Rate (BER)
Added Deterministic Jitter
Added Random Jitter
Differential Intrapair Skew
Differential Interpair Skew¹
INPUT CHARACTERISTICS
Input Voltage Swing
Input Common-Mode Voltage (VICM)
OUTPUT CHARACTERISTICS
High Voltage Level
Low Voltage Level
Rise/Fall Time (20% to 80%)
TERMINATION
Input Resistance
Output Resistance
POWER SUPPLY
AVCC
QUIESCENT CURRENT²
AVCC
VTTI
VTTO
POWER DISSIPATION³
SOURCE SELECT INTERFACE
Input High Voltage (VIH)
Input Low Voltage (VIL)
Conditions/Comments
NRZ
At output
At output
Differential
Single-ended high speed channel
Single-ended high speed channel
Single-ended
Single-ended
Operating range
S_SEL
S_SEL
Min
Typ Max
Unit
2.25
Gbps
10^−9
25
ps (p-p)
1
ps (rms)
1
ps
30
ps
150
AVCC − 800
1200
mV
AVCC
mV
AVCC
mV
AVCC − 600
AVCC − 400 mV
75
178
ps
50
Ω
50
Ω
3
3.3 3.6
V
50 70
mA
40 54
mA
40 65
mA
429
mW
2
V
0.8
V
1 _{Differential interpair skew is measured between the TMDS pairs of a single link.}
2 _{Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI link is deactivated. Minimum and}
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.
3 _{The total power dissipation excludes power dissipated in the 50 Ω off-chip loads.}
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