AD7843 Datasheet, PDF (3/16 Pages) Analog Devices – Touch Screen Digitizer

AD7843
TIMING SPECIFICATIONS1
(T_A = T_MIN to T_MAX, unless otherwise noted; V_CC = 2.7 V to 3.6 V, V_REF = 2.5 V)
Parameter
f_DCLK ²
t_ACQ
t₁
t₂
t₃₃
t₄
t₅
t₆
t₇
t₈
t₉₃
t₁₀
t₁₁
t₁₂₄
Limit at T_MIN, T_MAX
10
2
1.5
10
60
60
200
200
60
10
10
200
0
200
200
Unit
kHz min
MHz max
µs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
Description
Acquisition Time
CS Falling Edge to First DCLK Rising Edge
CS Falling Edge to BUSY Three-State Disabled
CS Falling Edge to DOUT Three-State Disabled
DCLK High Pulsewidth
DCLK Low Pulsewidth
DCLK Falling Edge to BUSY Rising Edge
Data Setup Time Prior to DCLK Rising Edge
Data Valid to DCLK Hold Time
Data Access Time after DCLK Falling Edge
CS Rising Edge to DCLK Ignored
CS Rising Edge to BUSY High Impedance
CS Rising Edge to DOUT High Impedance
NOTES
1_{Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V CC) and timed from a voltage level of 1.6 V.}
2_{Mark/Space ratio for the SCLK input is 40/60 to 60/40.}
3_{Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 2.0 V.}
4_{t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated}
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t ₁₂, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200␮A
I_OL
TO
OUTPUT
PIN
C_L
50pF
200␮A
I_OH
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. 0
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