AD7841 Datasheet, PDF (3/12 Pages) Analog Devices – Octal 14-Bit, Parallel Input, Voltage-Output DAC

AD7841
AC PERFORMANCE CHARACTERISTICS (These characteristics are included for Design Guidance and are not subject
to production testing.)
Parameter
A&B
Versions Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 31
Slew Rate
0.7
Digital-to-Analog Glitch Impulse 230
Channel-to-Channel Isolation 99
DAC-to-DAC Crosstalk
40
Digital Crosstalk
0.2
Digital Feedthrough
0.1
Output Noise Spectral Density
␣ ␣ @ 1 kHz
200
µs typ
V/µs typ
nV-s typ
dB typ
nV-s typ
nV-s typ
nV-s typ
Full-Scale Change to ± 1/2 LSB. DAC Latch Contents Alternately
Loaded with All 0s and All 1s
Measured with V_REF(+) = +5 V, V_REF(–) = –5 V. DAC Latch
Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent
on Load Conditions
See Terminology
See Terminology
Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Effect of Input Bus Activity on DAC Output Under Test
nV/√Hz typ All 1s Loaded to DAC. V_REF(+) = V_REF(–) = 0 V
TIMING SPECIFICATIONS1, 2
(V_CC = +5 V ؎ 5%; V_DD = +15 V ؎ 10%; V_SS = –15 V ؎ 10%; GND = DUTGND = 0 V)
Parameter
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
Limit at T_MIN, T_MAX
15
0
50
50
0
0
20
0
31
300
50
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
ns max
ns min
Description
Address to WR Setup Time
Address to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
CS to WR Setup Time
WR to CS Hold Time
Data Setup Time
Data Hold Time
Settling Time
CLR Pulse Activation Time
LDAC Pulsewidth Low
NOTES
1_{All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.}
2_{Rise and fall times should be no longer than 50 ns.}
Specifications subject to change without notice.
REV. 0
A0, A1, A2
CS
WR
DATA
V_OUT
CLR
t₁
t₂
t₅
t₆
t₃
t₄
t₇
t₈
t₉
t₁₀
V_OUT
LDAC
t₁₁
Figure 1. Timing Diagram
–3–