AD7827_15 Datasheet, PDF (3/12 Pages) Analog Devices – 3 V/5 V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC

AD7827
Parameter
Version B
POWER SUPPLY
V_DD
I_DD
Normal Operation
Power-Down
Power Dissipation
Normal Operation
Power-Down
200 kSPS
1 MSPS
4.5
5.5
2.7
3.3
10
1
30
9.58
47.88
NOTES
1_{See Terminology section of this data sheet.}
2_{Refer to the Analog Input section for an explanation of the Analog Input(s).}
Specifications subject to change without notice.
Units
V min
V max
V min
V max
mA max
µA max
mW max
mW max
mW max
Test Conditions/Comments
5 V ± 10% For Specified Performance
3 V ± 10% For Specified Performance
8 mA Typically
Logic Inputs = 0 V or V_DD
V_DD = 3 V
Typically 24 mW
TIMING CHARACTERISTICS1, 2
(V_REFIN/REFOUT = 2.5 V, all specifications –40؇C to +105؇C, unless otherwise noted)
Parameter 5 V ؎ 10%
3 V ؎ 10%
Units Conditions/Comments
t_CONVERT
t₁
t₂
t₃₃
t₄
t₅₃
t₆₃
t₇
t₈
t₉₄
t₁₀
t₁₁
t_POWER-UP
t_POWER-UP
420
20
t_CONVERT+t₃
t_CONVERT+t₃+t₇+t₈
14
14
20
14
25
25
20
35
20
420
20
t_CONVERT+t₃
t_CONVERT+t₃+t₇+t₈
18
18
20
18
25
25
20
35
20
ns max
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
30
30
ns min
1
1
µs max
25
25
µs max
Conversion Time.
Minimum CONVST Pulsewidth.
Falling edge of CONVST to falling edge of RFS.
Rising edge of SCLK to falling edge of RFS.
Rising edge of SCLK to rising edge of RFS.
Rising edge of SCLK to high impedance disabled.
Rising edge of SCLK to D_OUT valid delay.
Minimum high SCLK pulse duration.
Minimum low SCLK pulse duration.
Bus relinquish time after SCLK falling edge.
Maximum delay from falling edge CONVST to rising edge RFS if
RFS reset by CONVST.
Minimum time between end of serial read and next falling edge of
CONVST.
Power-up time from rising edge of CONVST using external 2.5 V
reference.
Power-up time from rising edge of CONVST using on-chip reference.
NOTES
1_{Sample tested to ensure compliance.}
2_{See Figures 13, 14 and 15.}
3_{Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V DD = 5 V ± 10% and time required for an}
output to cross 0.4 V or 2.0 V with V_DD = 3 V ± 10%.
4_{Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back}
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t ₉, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
200␮A
I_OL
TO
OUTPUT
PIN
C_L
50pF
200␮A
I_OH
+2.1V
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. 0
–3–