AD7813 Datasheet, PDF (3/11 Pages) Analog Devices – +2.7 V to +5.5 V, 400 kSPS 8-/10-Bit Sampling ADC

AD7813
TIMING CHARACTERISTICS^{1, 2} (–40؇C to +105؇C, unless otherwise noted)
Parameter
t_POWER-UP
t₁
t₂
t₃
t₄
t₅
t₆₃
t_73, ⁴
t₈
t₉₃
V_DD = 3 V ؎ 10%
1
2.3
20
30
0
0
10
10
5
10
50
V_DD = 5 V ؎ 10%
1
2.3
20
30
0
0
10
10
5
10
50
Unit
µs (max)
µs (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
Conditions/Comments
Power-Up Time of AD7813 after Rising Edge of CONVST.
Conversion Time.
CONVST Pulsewidth.
CONVST Falling Edge to BUSY Rising Edge Delay.
CS to RD Setup Time.
CS Hold Time after RD High.
Data Access Time after RD Low.
Bus Relinquish Time after RD High.
Minimum Time Between MSB and LSB Reads.
Rising Edge of CS or RD to Falling Edge of CONVST Delay.
NOTES
1_{Sample tested to ensure compliance.}
2_{See Figures 12, 13 and 14.}
3_{These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and}
0.4 V or 2 V for V_DD = 3 V ± 10%.
4_{Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back}
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t ₇, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
ABSOLUTE MAXIMUM RATINGS*
V_DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND
(CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, V_DD + 0.3 V
Digital Output Voltage to DGND
(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, V_DD + 0.3 V
REF_IN to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD + 0.3 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD + 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ_JA Thermal Impedance . . . . . . . . . . . . . . . . . . . +105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ_JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ_JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≥4 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
200␮A
I_OL
TO
OUTPUT
PIN
C_L
50pF
200␮A
I_OH
+1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
ORDERING GUIDE
Model
Linearity
Error Package
(LSB) Description
Package
Option
AD7813YN ± 1 LSB
AD7813YR ± 1 LSB
AD7813YRU ± 1 LSB
Plastic DIP
N-16
Small Outline IC
R-16A
Thin Shrink Small Outline RU-16
(TSSOP)
REV. B
–3–