AD7811_15 Datasheet, PDF (3/24 Pages) Analog Devices – 2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs

AD7811/AD7812
Parameter
Y Version
Unit
Test Conditions/Comments
POWER SUPPLY
V_DD
2.7
5.5
I_DD
Normal Operation
3.5
Power-Down
Full Power-Down
1
Partial Power-Down (Internal Ref)
350
Power Dissipation
Normal Operation
10.5
Auto Full Power-Down
Throughput 1 kSPS
31.5
Throughput 10 kSPS
315
Throughput 100 kSPS
3.15
Partial Power-Down (Internal Ref)
1.05
Full Power-Down
3
V min
V max
mA max
µA max
µA max
mW max
µW max
µW max
mW max
mW max
µW max
For Specified Performance
Digital Inputs = 0 V or V_DD
See Power-Up Times Section
V_DD = 3 V
See Power vs. Throughput Section
NOTES
1_{See Terminology.}
2_{Sample tested during initial release and after any redesign or process change that may affect this parameter.}
Specifications subject to change without notice.
TIMING CHARACTERISTICS^{1, 2} (V_DD = 2.7 V to 5.5 V, V_REF = V_DD [EXT] unless otherwise noted)
Parameter
Y Version
Unit
Conditions/Comments
t_POWER-UP
1.5
t₁
2.3
t₂
20
t₃
25
t₄
25
t₅₃
5
t₆₃
5
t₇₃
10
t₈
10
t₉
5
t 3, 4
10
20
t₁₁
100
µs (max)
µs (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (min)
Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST
Conversion Time
CONVST Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
RFS Rising Edge to SCLK Rising Edge Setup Time
TFS Falling Edge to SCLK Falling Edge Setup Time
SCLK Rising Edge to Data Out Valid
DIN Data Valid to SCLK Falling Edge Setup Time
DIN Data Valid after SCLK Falling Edge Hold Time
SCLK Rising Edge to DOUT High Impedance
DOUT High Impedance to CONVST Falling Edge
NOTES
1_{Sample tested to ensure compliance.}
2_{See Figures 16, 17 and 18.}
3_{These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and}
0.4 V or 2 V for V_DD = 3 V ± 10%.
4_{Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back}
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t ₁₁, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
200␮A
I_OL
TO
OUTPUT
PIN
C_L
50pF
200␮A
I_OH
2.1V
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. C
–3–