AD7776 Datasheet, PDF (3/12 Pages) Analog Devices – LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs

AD7776/AD7777/AD7778
TIMING SPECIFICATIONS1, 2
(V_CC = +5 V ؎ 5%; AGND = DGND = 0 V; all specifications T_MIN to T_MAX unless otherwise noted.)
Parameter
Label Limit at T_MIN to T_MAX Units
Test Conditions/Comments
INTERFACE TIMING
CS Falling Edge to WR or RD Falling Edge t₁
WR or RD Rising Edge to CS Rising Edge
t₂
WR Pulse Width
t₃
CS or RD Active to Valid Data³
t₄
Bus Relinquish Time after RD⁴
t₅
Data Valid to WR Rising Edge
t₆
Data Valid after WR Rising Edge
t₇
WR Rising Edge to BUSY Falling Edge
t₈
WR Rising Edge to BUSY Rising Edge or
INT Falling Edge
t₉
t₁₀
WR or RD Falling Edge to INT Rising Edge t₁₁
0
0
53
60
10
45
55
10
1.5 t_CLKIN
2.5 t_CLKIN + 70
19.5 t_CLKIN + 70
33.5 t_CLKIN + 70
60
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
Timed from Whichever Occurs Last
CR9 = 0
ns max
ns max
ns max
Single Conversion, CR6 = 0
Double Conversion, CR6 = 1
CR9 = 1
NOTES
1_{See Figures 1 to 3.}
2_{Timing specifications in bold print are 100% production tested. All other times are guaranteed by design, not production tested. All input signals are specified with}
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3_{t4 is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.}
4_{t5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back}
to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t ₅ quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
CS
RD
DB0–DB9
t1
t4
t2
t5
WR, RD
BUSY
(CR8 = 0)
INT
(CR8 = 1)
t₃
t₈
FIRST
CONVERSION
FINISHED
(CR6 = 0)
t₉
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
t₁₁
t₁₀
t₉
t₁₀
Figure 1. Read Cycle Timing
Figure 3. BUSY/INT Timing
t1
CS
WR
DB0–DB9
t3
t6
t2
t7
Figure 2. Write Cycle Timing
I_OL
1.6mA
DB n
C_OUT
100pF
+2.1V
I_OH
200µA
Figure 4. Load Circuit for Bus Timing Characteristics
REV. 0
–3–