AD7710AR-REEL7 Datasheet, PDF (3/32 Pages) Analog Devices – Signal Conditioning ADC

AD7710
Parameter
A, S Versions¹
Unit
Conditions/Comments
REFERENCE OUTPUT
Output Voltage
Initial Tolerance @ 25°C
Drift
Output Noise
Line Regulation (AV_DD)
Load Regulation
External Current
V_BIAS INPUT¹²
Input Voltage Range
V_BIAS Rejection
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V_INL, Input Low Voltage
V_INH, Input High Voltage
MCLK IN Only
V_INL, Input Low Voltage
V_INH, Input High Voltage
LOGIC OUTPUTS
V_OL, Output Low Voltage
V_OH, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance¹³
2.5
V nom
±1
% max
20
ppm/°C typ
30
µV typ
Peak-peak Noise 0.1 Hz to 10 Hz Bandwidth
1
mV/V max
1.5
mV/mA max Maximum Load Current 1 mA
1
mA max
AV_DD – 0.85 × V_REF
or AV_DD – 3.5
or AV_DD – 2.1
V_SS + 0.85 × V_REF
or V_SS + 3
or V_SS + 2.1
65 to 85
V max
V max
V min
V min
dB typ
See V_BIAS Input Section
Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AV_DD/V_SS
Whichever Is Smaller; +5 V/0 V Nominal AV_DD/V_SS
See V_BIAS Input Section
Whichever Is Greater; +5 V/–5 V or +10 V/0 V
Nominal AV_DD/V_SS
Whichever Is Greater; +5 V/0 V Nominal AV_DD/V_SS
Increasing with Gain
± 10
µΑ max
0.8
V max
2.0
V min
0.8
V max
3.5
V min
0.4
DV_DD – 1
± 10
9
V max
V min
µA max
pF typ
I_SINK = 1.6 mA
I_SOURCE = 100 µA
TRANSDUCER BURNOUT
Current
4.5
Initial Tolerance @ 25°C
± 10
Drift
0.1
µA nom
% typ
%/°C typ
COMPENSATION CURRENT
Output Current
Initial Tolerance @ 25°C
Drift
Line Regulation (AV_DD)
Load Regulation
Output Compliance
20
±4
35
20
20
AV_DD – 2
µA nom
µA max
ppm/°C typ
nA/V max
nA/V max
V max
AV_DD = +5 V
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit^l4
Negative Full-Scale Calibration Limit^l4
Offset Calibration Limits¹⁵
Input Span¹⁵
(1.05 × V_REF)/GAIN
–(1.05 × V_REF)/GAIN
–(1.05 × V_REF)/GAIN
0.8 × V_REF/GAIN
(2.1 × V_REF)/GAIN
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12_{The AD7710 is tested with the following VBIAS voltages. With AVDD = 5 V and VSS = 0 V, VBIAS = 2.5 V; with AVDD = 10 V and VSS = 0 V, VBIAS = 5 V; and with}
AV_DD = 5 V and V_SS = –5 V, V_BIAS = 0 V.
13_{Guaranteed by design, not production tested.}
14_{After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale then the device will}
output all 0s.
15_{These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than VSS – 30 mV.}
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
REV. G
–3–