AD767JNZ Datasheet, PDF (3/8 Pages) Analog Devices – Microprocessor-Compatible 12-Bit D/A Converter

ABSOLUTE MAXIMUM RATINGS*
V_CC to Power Ground . . . . . . . . . . . . . . . . . . . . .0 V to +18 V
V_EE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
Digital Inputs (Pins 11, 13–24)
to Power Ground . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . ± 12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . ± 12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 24 V
TIMING SPECIFICATIONS
(All Models, T_A = 25°C, V_CC = +12 V or +15 V,
V_EE = –12 V or –15 V)
AD767
Ref Out, V_OUT (Pins 6, 9) . . . Indefinite short to power ground
Momentary Short to V_CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Symbol Parameter
Min Typ Max
t_DS
Data Valid to End of CS
(–25°C to +85°C)
(–55°C to +125°C)
40 –
60 –
90 –
– ns
– ns
– ns
t_DH
Data Hold Tiıne
(–25°C to +85°C)
(–55°C to +125°C)
10 –
10 –
20 –
– ns
– ns
– ns
t_CS
CS Pulse Width
(–25°C to +85°C)
(–55°C to +125°C)
40 –
60 –
90 –
– ns
– ns
– ns
t_SETT Output Voltage Settling Time* – 2 4 µs
*t_SETT is measured referenced to the leading edge of t_CS. If t_CS > t_DS, then
t_SETT is measured referenced to the beginning of Data Valid.
PIN CONFIGURATION
DIP
PLCC
REV. A
ORDERING GUIDE
Model¹ Package
Linearity Gain T.C.
Temperature Error Max Max
Range ؇C
T_MIN–T_MAX ppm/؇C
AD767JN Plastic DIP 0 to +70
± 1 LSB
30
AD767JP PLCC
0 to +70
± 1 LSB
30
AD767KN Plastic DIP 0 to +70
± 1/2 LSB 15
AD767KP PLCC
0 to +70
± 1/2 LSB 15
AD767AD Ceramic DIP –25 to +85 ± 1 LSB
30
AD767BD Ceramic DIP –25 to +85 ± 1/2 LSB 15
AD767SD/
883B Ceramic DIP –55 to +125 Note 2
Note 2
AD767A
Chips N/A
–25 to +85 ± 1 LSB
30
NOTES
1_{D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.}
2_{For details on grade and package offerings screened in accordance with MIL-STD-883, refer to}
the Analog Devices Military Products Databook or current AD767/883B data sheet.
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