AD7665 Datasheet, PDF (3/24 Pages) Analog Devices – 16-Bit, 570 kSPS CMOS ADC

AD7665
Parameter
Conditions
Min
Typ
Max
POWER SUPPLIES (Continued)
Power Dissipation^{5, 6}
In Power-Down Mode⁸
444 kSPS Throughput⁷
100 SPS Throughput⁷
570 kSPS Throughput⁴
64
74
15
93
107
7
TEMPERATURE RANGE⁹
Specified Performance
T_MIN to T_MAX
–40
+85
NOTES
1_{LSB means Least Significant Bit. With the ± 5 V input range, one LSB is 152.588 µV.}
2_{See Definition of Specifications section. These specifications do not include the error contribution from the external reference.}
3_{All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.}
4_{In warp mode.}
5_{Tested in parallel reading mode.}
6_{Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. See Power Dissipation section.}
7_{In impulse mode.}
8_{With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND respect ively.}
9_{Contact factory for extended temperature range.}
Specifications subject to change without notice.
Unit
mW
µW
mW
µW
°C
Input Voltage
Range
IND (4R)
± 4 REF
V_IN
± 2 REF
V_IN
± REF
V_IN
0 V to 4 REF
V_IN
0 V to 2 REF
V_IN
0 V to REF
V_IN
NOTES
1_{Typical analog input impedance.}
2_{For this range the input is high impedance.}
Table I. Analog Input Configuration
INC (4R)
INGND
V_IN
V_IN
V_IN
V_IN
V_IN
INB (2R)
INGND
INGND
V_IN
INGND
V_IN
V_IN
INA (R)
REF
REF
REF
INGND
INGND
V_IN
Input
Impedance¹
5.85 kΩ
3.41 kΩ
2.56 kΩ
3.41 kΩ
2.56 kΩ
Note 2
TIMING SPECIFICATIONS (–40؇C to +85؇C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Refer to Figures 11 and 12
Convert Pulsewidth
Time Between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read after
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figures 17 and 18 (Master Serial Interface Modes)²
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay (Read During Convert)
(Warp Mode/Normal Mode/Impulse Mode)
Symbol
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
t₁₇
Min
5
1.75/2/2.25
10
1
10
20
5
Typ
Max
Unit
ns
Note 1
µs
30
ns
0.75/1/1.25 µs
2
ns
ns
0.75/1/1.25 µs
µs
ns
0.75/1/1.25 µs
ns
40
ns
15
ns
10
ns
10
ns
10
ns
25/275/525
ns
REV. 0
–3–