AD7091R Datasheet, PDF (3/20 Pages) Analog Devices – 1 MSPS, Ultralow Power, 12-Bit ADC in 10-Lead LFCSP and MSOP

Data Sheet
AD7091R
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, VREF = 2.5 V internal reference, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C,
unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE¹
Signal-to-Noise Ratio (SNR)²
Signal-to-Noise-and-Distortion Ratio (SINAD)²
Total Harmonic Distortion (THD)²
Spurious Free Dynamic Range (SFDR)²
Aperture Delay²
Aperture Jitter²
Full Power Bandwidth²
DC ACCURACY
Resolution
Integral Nonlinearity (INL)^{2, 3}
Differential Nonlinearity (DNL)²
Offset Error²
Gain Error²
Total Unadjusted Error (TUE)²
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance⁴
VOLTAGE REFERENCE INPUT/OUTPUT
REFOUT
REFIN
Drift
LOGIC INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance (CIN)⁴
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating State Leakage Current
Floating State Output Capacitance⁴
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time^{2, 4}
Throughput Rate
Test Conditions/Comments
fIN = 10 kHz sine wave
fSAMPLE = 500 kSPS
At −3 dB
At −0.1 dB
Min
Typ
Max
66.5
69
67.5
70
66
69
−84
−79
−85
−78
5
40
7.5
1.2
12
VDRIVE ≤ 3.3 V
VDRIVE > 3.3 V with external VREF
Guaranteed no missing codes to 12 bits
±0.8
±1
±1
±0.3
±0.9
±0.6
±2
±0.8
±3
−2
0
VREF
±1
During acquisition phase
7
Outside acquisition phase
1
2.485
2.5
2.525
2.7
VDD
±4.5
±25
Typically 10 nA, VIN = 0 V or VDRIVE
0.7 × VDRIVE
0.3 × VDRIVE
±1
5
ISOURCE = 200 µA
ISINK = 200 µA
VDRIVE − 0.2
0.4
±1
5
Straight binary
650
Full-scale step input
350
1
Unit
dB
dB
dB
dB
dB
ns
ps
MHz
MHz
Bits
LSB
LSB
LSB
LSB
LSB
LSB
V
µA
pF
pF
V
V
ppm/°C
V
V
µA
pF
V
V
µA
pF
ns
ns
MSPS
Rev. 0 | Page 3 of 20