AD698_15 Datasheet, PDF (3/12 Pages) Analog Devices – Universal LVDT Signal Conditioner

AD698
NOTES
1_{A and B represent the Mean Average Deviation (MAD) of the detected sine waves V A and VB. The polarity of VOUT is affected by the sign of the A comparator, i.e.,}
multiply V_OUT × +1 for A_COMP+ > A_COMP–, and V_OUT × –1 for A_COMP– > A_COMP+.
2_{Nonlinearity of the AD698 only in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD698 output voltage from a}
straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage.
3_{See Transfer Function.}
4_{For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm.}
5_{Output ripple is a function of the AD698 bandwidth determined by C1 and C2. A 1000 pF capacitor should be connected in parallel with R2 to reduce the output}
ripple. See Figures 7, 8 and 13.
6_{R1 is shown in Figures 7, 8 and 13.}
7_{Excitation voltage drift is not an important specification because of the ratiometric operation of the AD698.}
8_{From TMIN to TMAX the overall error due to the AD698 alone is determined by combining gain error, gain drift and offset drift. For example, the typical overall}
error for the AD698AP from T_MIN to T_MAX is calculated as follows: Overall Error = Gain Error at +25°C (± 0.2% Full Scale) + Gain Drift from –40°C to +25°C
(20 ppm/°C × 65°C) + Offset Drift from –40°C to +25°C (5 ppm/°C × 65°C) = ± 0.36% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels.
All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (+V_S to –V_S) . . . . . . . . . . . . . . . . . 36 V
Storage Temperature Range
P Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Q Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD698SQ . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
AD698AP . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Power Dissipation Derates above +65°C
P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C
Q Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C
THERMAL CHARACTERISTICS
θ_JC
P Package 30°C/W
Q Package 26°C/W
θ_JA
60°C/W
62°C/W
Model
AD698AP
AD698SQ
ORDERING GUIDE
Package Description Package Option
28-Pin PLCC
24-Pin Double Cerdip
P-28A
Q-24A
CONNECTION DIAGRAMS
28-Pin PLCC
4 3 2 1 28 27 26
LEV1 5
LEV2 6
FREQ1 7
FREQ2 8
NC 9
BFILT1 10
BFILT2 11
AD698
TOP VIEW
(Not to Scale)
25 NC
24 SIG REF
23 SIG OUT
22 FEEDBACK
21 OUT FILT
20 AFILT1
19 AFILT2
12 13 14 15 16 17 18
NC = NO CONNECT
24-Pin Cerdip
–V_S 1
EXC1 2
24 +V_S
23 OFFSET1
EXC2 3
22 OFFSET2
LEV1 4
21 SIG REF
LEV2 5 _AD698 20 SIG OUT
FREQ1 6 _{TOP VIEW} 19 FEEDBACK
FREQ2 7 ^{(Not to Scale)} 18 OUT FILT
BFILT1 8
17 AFILT1
BFILT2 9
16 AFILT2
–BIN 10
15 –ACOMP
+BIN 11
14 +ACOMP
–AIN 12
13 +AIN
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD698 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–