AD669ARZ Datasheet, PDF (3/12 Pages) Analog Devices – Monolithic 16-Bit DACPORT

AD669
AC PERFORMANCE CHARACTERISTICS (With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
T_MIN ≤ T_A ≤ T_MAX, V_CC = +15 V, V_EE = –15 V, V_LL = +5 V except where noted.)
Parameter
Limit Units
Test Conditions/Comments
Output Settling Time
(Time to ± 0.0008% FS
with 2 kΩ, 1000 pF Load)
Total Harmonic Distortion + Noise
A, B, S Grade
A, B, S Grade
A, B, S Grade
Signal-to-Noise Ratio
Digital-to-Analog Glitch Impulse
13
8
10
6
8
2.5
0.009
0.07
7.0
83
15
µs max
µs typ
µs typ
µs typ
µs typ
µs typ
% max
% max
% max
dB min
nV-s typ
20 V Step, T_A = +25°C
20 V Step, T_A = +25°C
20 V Step, T_MIN ≤ T_A ≤ T_MAX
10 V Step, T_A = +25°C
10 V Step, T_MIN ≤ T_A ≤ T_MAX
1 LSB Step, T_MIN ≤ T_A ≤ T_MAX
0 dB, 1001 Hz; Sample Rate = 100 kHz; T_A = +25°C
–20 dB, 1001 Hz; Sample Rate = 100 kHz; T_A = +25°C
–60 dB, 1001 Hz; Sample Rate = 100 kHz; T_A = +25°C
T_A = +25°C
DAC Alternately Loaded with 8000H and 7FFFH
Digital Feedthrough
2
nV-s typ
DAC Alternately Loaded with 0000H and FFFFH; CS High
Output Noise Voltage
Density (1 kHz – 1 MHz)
120
nV/√Hz typ
Measured at V_OUT, 20 V Span; Excludes Reference
Reference Noise
125
nV/√Hz typ Measured at REF OUT
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed. Those shown in boldface are tested on all production units.
TIMING CHARACTERISTICS
V_CC = +15 V, V_EE = –15 V, V_LL = +5 V, V_HI = 2.4 V, V_LO = 0.4 V
t_CS
CS
Limit
Limit
–40؇C to
Limit
–55؇C to
t_L1
L1
Parameter +25؇C
+85؇C
+125؇C Units
(Figure la)
t_CS
40
50
55
ns min
t_LI
40
50
55
ns min
t_DS
30
35
40
ns min
t_DH
10
10
15
ns min
t_LH
90
110
120
ns min
t_LW
40
45
45
ns min
(Figure lb)
t_LOW
130
150
t_HIGH
t_DS
t_DH
40
45
120
140
10
10
165
ns min
45
ns min
150
ns min
15
ns min
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. Those shown in boldface are tested
on all production units.
DATA
LDAC
t_DS t _DH
t _LW
t _LH
Figure 1a. AD669 Level Triggered Timing Diagram
CS AND/OR
L1, LDAC
t _LOW
t_HIGH
DATA
t _DS
t _DH
TIE CS AND/OR L1 TO GROUND OR TOGETHER WITH LDAC
Figure 1b. AD669 Edge Triggered Timing Diagram
REV. A
–3–