AD598_15 Datasheet, PDF (3/16 Pages) Analog Devices – LVDT Signal Conditioner

AD598
NOTES
1_{VA and VB represent the Mean Average Deviation (MAD) of the detected sine waves. Note that for this Transfer Function to linearly represent positive displacement,}
the sum of V_A and V_B of the LVDT must remain constant with stroke length. See “Theory of Operation.” Also see Figures 7 and 12 for R2.
2_{From TMIN, to TMAX, the overall error due to the AD598 alone is determined by combining gain error, gain drift and offset drift. For example the worst case overall}
error for the AD598AD from T_MIN to T_MAX is calculated as follows: overall error = gain error at +25°C (± 1% full scale) + gain drift from –40°C to +25°C (50 ppm/°C
of FS × +65°C) + offset drift from –40°C to +25°C (50 ppm/°C of FS × +65°C) = ± 1.65% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale.
Full scale is defined as the voltage difference between the maximum positive and maximum negative output.
3_{Nonlinearity of the AD598 only, in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD598 output voltage from a}
straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage.
4_{See Transfer Function.}
5_{This offset refers to the (VA–VB)/(VA+VB) input spanning a full-scale range of ± 1. [For (VA–VB)/(VA+VB) to equal +1, VB must equal zero volts; and correspondingly}
for (V_A–V_B)/(V_A+V_B) to equal –1, V_A must equal zero volts. Note that offset errors do not allow accurate use of zero magnitude inputs, practical inputs are limited to
100 mV rms.] The ± 1 span is a convenient reference point to define offset referred to input. For example, with this input span a value of R2 = 20 k Ω would give
V_OUT span a value of ± 10 volts. Caution, most LVDTs will typically exercise less of the ((V _A–V_B))/((V_A+V_B)) input span and thus require a larger value of R2 to
produce the ± 10 V output span. In this case the offset is correspondingly magnified when referred to the output voltage. For example, a Schaevitz E100 LVDT
requires 80.2 kΩ for R2 to produce a ± 10.69 V output and (V_A–V_B)/(V_A+V_B) equals 0.27. This ratio may be determined from the graph shown in Figure 18,
(V_A–V_B)/(V_A+V_B) = (1.71 V rms – 0.99 V rms)/(1.71 V rms + 0.99 V rms). The maximum offset value referred to the ± 10.69 V output may be determined by
multiplying the maximum value shown in the data sheet (± 1% of FS by 1/0.27 which equals ± 3.7% maximum. Similarly, to determine the maximum values of offset
drift, offset CMRR and offset PSRR when referred to the ± 10.69 V output, these data sheet values should also be multiplied by (1/0.27). For this example for the
AD598AD the maximum values of offset drift, PSRR offset and CMRR offset would be: 185 ppm/ °C of FS; 741 ppm/V and 741 ppm/V respectively when referred
to the ± 10.69 V output.
6_{For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm.}
7_{Output ripple is a function of the AD598 bandwidth determined by C2, C3 and C4. See Figures 16 and 17.}
8_{R1 is shown in Figures 7 and 12.}
9_{Excitation voltage drift is not an important specification because of the ratiometric operation of the AD598.}
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
THERMAL CHARACTERISTICS
θ_JC
θ_JA
SOIC Package
22°C/W
Side Brazed Package 25°C/W
80°C/W
85°C/W
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage +V_S to –V_S . . . . . . . . . . . . . . . . . +36 V
Storage Temperature Range
R Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
D Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD598JR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD598AD . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Power Dissipation Up to +65°C . . . . . . . . . . . . . . . . . . . 1.2 W
Derates Above +65°C . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C
Model
AD598JR
AD598AD
ORDERING GUIDE
Temperature
Range
0°C to +70°C
–40°C to +85C
Package
Description
SOIC
Ceramic DIP
Package
Option
R-20
D-20
–V_S 1
EXC 1 2
20 +V_S
19 OFFSET 1
EXC 2 3
18 OFFSET 2
LEVEL 1 4
LEVEL 2 5
FREQ 1 6
FREQ 2 7
AD598
TOP VIEW
(Not to Scale)
17 SIGNAL REFERENCE
16 SIGNAL OUTPUT
15 FEEDBACK
14 OUTPUT FILTER
B1 FILTER 8
13 A1 FILTER
B2 FILTER 9
12 A2 FILTER
V_B 10
11 V_A
REV. A
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