ADXL354 Datasheet, PDF (29/42 Pages) Analog Devices – Hermetic package offers excellent long-term stability

Data Sheet
ADXL354/ADXL355
EXTERNAL SYNCHRONIZATION AND
INTERPOLATION
There are three possible synchronization options for the ADXL355,
shown in Figure 72 to Figure 74. For clarity, the clock frequencies
and delays are drawn to scale. The labels in Figure 72 to Figure 74
are defined as follows:
• Internal ODR is the alignment of the decimated output
data based on the internal clock.
• ADC clock shows the internal master clock rate
• DRDY is an output indicator signaling a sample is ready.
The three modes are include as follows:
• No external synchronization (internal clocks used)
• Synchronization with interpolation filter enabled
• Sync with an external sync and clock signals, no
interpolation filter
EXT_SYNC = 00—No External Sync or Interpolation
For this case, an internal clock that serves as the synchronization
master generates the data. No external signals are required, and
this is used commonly when the external processor retrieves
data from the device asynchronously and absolute synchronization
to an external source is not required. Use Register 0x28 to program
the ODR.
The device outputs a DRDY (active high) to signal that a new
sample is available, and data is retrieved from the real-time
registers or the FIFO. The group delay is based on the
decimation setting as shown in Table 9.
EXT_SYNC = 10—External Sync with Interpolation
In this case, the internal clock generates data; however, an
interpolation filter provides additional time resolution of 64
times the programmed ODR. Synchronization using interpolation
filters and an external ODR clock is commonly used when the
external processor can provide a synchronization signal (which
is asynchronous to the internal clock) at the desired ODR.
Synchronization with the interpolation filter enabled
(EXT_SYNC = 10) allows the nonsynchronous external clock to
output data most closely associated with the external clock
rising edge. The interpolation filter provides a frequency
resolution related to ODR (see Table 11).
The advantage of this mode is that data is available at a user
defined sample rate and is asynchronous to the internal oscillator.
The disadvantage of this mode is that the group delay is increased,
and there is increased attenuation at the band edge. Additionally,
because there is a limit to the time resolution, there is some
distortion related to the mismatch of the external sync relative
to the internal oscillator. This mismatch degrades spectral
performance. The group delay is based on the decimation setting
and interpolation setting (see Table 11). Table 13 shows the delay
between the SYNC signal (input) to DRDY (output).
EXT_SYNC = 01—External Sync and External Clock
In this case, an external source provides an external clock at a
frequency of 4 × 64 × ODR. The external clock becomes the
master clock source for the device. In addition, an external
synchronization signal is needed to align the decimation filter
output to a specific clock edge, which provides full external
synchronization and is commonly used when a fixed external
clock captures and processes data, and asynchronous clock(s) are
not allowed. When using multiple sensors, synchronization with an
external master clock is beneficial and requires time alignment.
When configured for EXT_SYNC = 01 with an ODR of 4 kHz,
the user must supply an external clock at 1.024 MHz (64 × 4 ×
4 kHz) on the INT2 pin (Pin 13), and an external synchronization
on DRDY pin (Pin 14), as shown in Table 12.
Special restrictions when using this mode include the following:
• An external clock (EXT_CLK) must be provided as well as
an external sync.
• The frequency of EXT_CLK must be exactly 4 × 64 × ODR.
• The width of sync must be a minimum of four EXT_CLK
periods.
• The phase of sync must meet an approximate 25 ns setup
time to the EXT_CLK rising edge.
When using the EXT_SYNC mode and without providing sync,
the device runs on its own synchronization. Similarly, after
synchronization, the device continues to run synchronized to
the last sync pulse it received, which means that EXT_SYNC = 01
mode can be used with only a single synchronization pulse.
The interpolation filter provides a frequency resolution related to
the ODR (see Table 11). In this case, the data provided corresponds
to the external signal, which can be greater than the set ODR,
but the output pass band remains the same it was prior to the
interpolation filter.
Table 12. Multiplexing of INT2 and DRDY
Register or Bit Fields
EXT_CLK EXT_SYNC[1:0] INT_MAP[7:4]
0
00
0000
0
00
Not 0000
1
00
0000
1
00
Not 0000²
0
01
0000
0
01¹
Not 0000
Pins
INT2 (Pin 13) DRDY (Pin 14)
Low
DRDY
INT2
DRDY
EXT_CLK
DRDY
EXT_CLK
DRDY
DRDY
SYNC
INT2
SYNC
Rev. 0 | Page 29 of 42
Comments
Synchronization is to the internal clocks, and there is
no external clock synchronization.
These options reset the digital filters on every
synchronization pulse and are not recommended.