English
Language : 

ADT7516_15 Datasheet, PDF (29/44 Pages) Analog Devices – SPI-/IC-Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output
R/W
Address
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29 to
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31 to
0x4C
0x4D
0x4E
0x4F
Name
DAC C LSBs (ADT7516/ADT7517 only)
DAC C MSBs
DAC D LSBs (ADT7516/ADT7517 only)
DAC D MSBs
Control Configuration 1
Control Configuration 2
Control Configuration 3
DAC Configuration
LDAC Configuration
Interrupt Mask 1
Interrupt Mask 2
Internal Temp Offset
External Temp Offset
Internal Analog Temp Offset
External Analog Temp Offset
VDD VHIGH Limit
VDD VLOW Limit
Internal THIGH Limit
Internal TLOW Limit
External THIGH/AIN1 VHIGH Limits
External TLOW/AIN1 VLOW Limits
Reserved
AIN2 VHIGH Limit
AIN2 VLOW Limit
AIN3 VHIGH Limit
AIN3 VLOW Limit
AIN4 VHIGH Limit
AIN4 VLOW Limit
Reserved
Device ID
Manufacturer’s ID
Silicon Revision
0x50 to
0x7E
0x7F
0x80 to
0xFF
Reserved
SPI Lock Status
Reserved
Power-On
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xD8
0xD8
0xC7
0x62
0x64
0xC9
0xFF
0x00
0xFF
0x 00
0xFF
0x00
0xFF
0x00
0x03/0x0B/0x07
0x41
Check register
for current
silicon revision
0x00
0x00
0x00
Interrupt Status 1 Register (Read-Only) [Address 0x00]
This 8-bit read-only register reflects the status of some of the
interrupts that can cause the INT/INT pin to go active. This
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
D7 D6 D5 D4 D3 D2 D1 D0
01
01
01
01
01
01
01
01
1 Default settings at power-up.
ADT7516/ADT7517/ADT7519
Table 11.
Bit Function
D0 1 when the internal temperature value exceeds THIGH limit.
Any internal temperature reading greater than the set limit
causes an out-of-limit event.
D1 1 when internal temperature value exceeds TLOW limit. Any
internal temperature reading less than or equal to the set
limit causes an out-of-limit event.
D2 This status bit is linked to the configuration of Pin 7 and
Pin 8. If configured for external temperature sensor, this bit
is 1 when the external temperature value exceeds THIGH
limit. The default value for this limit register is –1°C, so any
external temperature reading greater than the set limit
causes an out-of-limit event. If configured for AIN1 and
AIN2, this bit is 1 when AIN1 input voltage exceeds VHIGH or
VLOW limits.
D3 1 when external temperature value exceeds TLOW limit. The
default value for this limit register is 0°C, so any external
temperature reading less than or equal to the set limit
causes an out-of-limit event.
D4 1 indicates a fault (open or short) for the external
temperature sensor.
D5 1 when AIN2 voltage is greater than its corresponding VHIGH
limit. 1 when AIN2 voltage is less than or equal to its
corresponding VLOW limit.
D6 1 when AIN3 voltage is greater than its corresponding VHIGH
limit. 1 when AIN3 voltage is less than or equal to its
corresponding VLOW limit.
D7 1 when AIN4 voltage is greater than its corresponding VHIGH
limit. 1 when AIN4 voltage is less than or equal to its
corresponding VLOW limit.
Interrupt Status 2 Register (Read-Only) [Address = 0x01]
This 8-bit read-only register reflects the status of the VDD
interrupt that can cause the INT/INT pin to go active. This
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
D7 D6 D5 D4 D3 D2 D1 D0
N/A N/A N/A 01 N/A N/A N/A N/A
1 Default settings at power-up.
Table 12.
Bit Function
D4 1 when VDD value is greater than its corresponding VHIGH
limit. 1 when VDD is less than or equal to its corresponding
VLOW limit.
Internal Temperature Value/VDD Value Register LSBs
(Read-Only) [Address = 0x03]
This 8-bit read-only register stores the two LSBs of the 10-bit
temperature reading from the internal temperature sensor and
the two LSBs of the 10-bit supply voltage reading.
D7 D6 D5 D4
N/A N/A N/A N/A
N/A N/A N/A N/A
1 Default settings at power-up.
D3 D2
V1 LSB
01
01
D1 D0
T1 LSB
01
01
Rev. B | Page 29 of 44