ADSP-BF523C_15 Datasheet, PDF (29/36 Pages) Analog Devices – Blackfin Embedded Processor with Codec

ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
System Clock Timing
Table 21. System Clock Timing
Parameter
Test Conditions¹ Min
t_XTIY
XTI/CODEC_MCLK system clock cycle time
72
t_MCLKDS
t_XTIH
t_XTIL
t_COP
t_COPDIV2
XTI/CODEC_MCLK duty cycle
XTI/CODEC_MCLK system clock pulse width high
XTI/CODEC_MCLK system clock pulse width low
CODEC_CLKOUT propagation delay from XTI/CODEC_MCLK falling edge
CLKODIV2 propagation delay from XTI/CODEC_MCLK falling edge
40:60
32
32
20
20
1 _{AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.}
Max
60:40
Unit
ns
ns
ns
ns
ns
CODEC_MCLK/XTI
tXTIH
tXTIY
tXTIL
tCOP
CODEC_CLKOUT
CODEC_CLKOUT/2
tCOPDIV2
Figure 22. System (CODEC_MCLK) Clock Timing
Rev. A | Page 29 of 36 | March 2010