AD5737_12 Datasheet, PDF (29/44 Pages) Analog Devices – Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output

Data Sheet
AD5737
Software Register
The software register allows the user to perform a software reset of
the part. This register is also used to set the user toggle bit, D11,
in the status register and as part of the watchdog timer feature
when that feature is enabled.
Bit D12 in the software register can be used to ensure that
communication has not been lost between the MCU and the
AD5737 and that the datapath lines are working properly (that
is, SDIN, SCLK, and SYNC).
Table 24. Programming the Software Register
D15
D14
D13
1
0
0
When the watchdog timer feature is enabled, the user must write
0x195 to Bits[D11:D0] of the software register within the timeout
period. If this command is not received within the timeout period,
the ALERT pin signals a fault condition. This command is only
required when the watchdog timer feature is enabled.
DC-to-DC Control Register
The dc-to-dc control register allows the user to configure the
dc-to-dc switching frequency and phase, as well as the maximum
allowable dc-to-dc output voltage. The dc-to-dc control register
options are shown in Table 26 and Table 27.
D12
User program
D11 to D0
Reset code/SPI code
Table 25. Software Register Bit Descriptions
Bit Name
Description
User Program
This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set to 1.
When this bit is set to 0, Bit D11 of the status register is also set to 0. This feature can be used to ensure that the SPI
pins are working correctly by writing a known bit value to this register and then reading back Bit D11 from the
status register.
Reset Code/SPI Code Option
Description
Reset code
Writing 0x555 to Bits[D11:D0] performs a software reset of the AD5737.
SPI code
If the watchdog timer feature is enabled, 0x195 must be written to the software register
(Bits[D11:D0]) within the programmed timeout period (see Table 21).
Table 26. Programming the DC-to-DC Control Register
D15
D14
D13
D12 to D7 D6
0
1
1
X¹
DC-DC comp
1 _{X = don’t care.}
D5 to D4
DC-DC phase
D3 to D2
DC-DC freq
D1 to D0
DC-DC MaxV
Table 27. DC-to-DC Control Register Bit Descriptions
Bit Name
Description
DC-DC Comp
Selects the internal compensation resistor or an external compensation resistor for the dc-to-dc converter. See the
DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section.
0 = selects the internal 150 kΩ compensation resistor (default).
1 = bypasses the internal compensation resistor. When this bit is set to 1, an external compensation resistor must
be used; this resistor is placed at the COMPDCDC_x pin in series with the 10 nF dc-to-dc compensation capacitor to
ground. Typically, a resistor of ~50 kΩ is recommended.
DC-DC Phase
User-programmable dc-to-dc converter phase (between channels).
00 = all dc-to-dc converters clock on the same edge (default).
01 = Channel A and Channel B clock on the same edge; Channel C and Channel D clock on the opposite edge.
10 = Channel A and Channel C clock on the same edge; Channel B and Channel D clock on the opposite edge.
11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other.
DC-DC Freq
Switching frequency for the dc-to-dc converter; this frequency is divided down from the internal 13 MHz oscillator
(see Figure 45 and Figure 46).
00 = 250 kHz ± 10%.
01 = 410 kHz ± 10% (default).
10 = 650 kHz ± 10%.
DC-DC MaxV
Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter.
00 = 23 V + 1 V/−1.5 V (default).
01 = 24.5 V ± 1 V.
10 = 27 V ± 1 V.
11 = 29.5 V ± 1 V.
Rev. B | Page 29 of 44