AD1938WBSTZ-RL Datasheet, PDF (29/32 Pages) Analog Devices – 4 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec

Data Sheet
ADDITIONAL MODES
The AD1938 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configu-
ration is applicable when the AD1938 master clock is generated
by the PLL with the DLRCLK as the PLL reference frequency.
DLRCLK
INTERNAL
DBCLK
DSDATAx
32 BITS
AD1938
To relax the requirement for the setup time of the AD1938 in
cases of high speed TDM data transmission, the AD1938 can
latch in the data using the falling edge of DBCLK. This effectively
dedicates the entire BCLK period to the setup time. This mode
is useful in cases where the source has a large delay time in the
serial data driver. Figure 28 shows this pipeline mode of data
transmission.
Both the BLCK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
INTERNAL
DBCLK
TDM-DSDATAx
DLRCLK
DBCLK
DSDATAx
Figure 27. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK. This Mode Is Also Available in the ADC Serial Data Port.)
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
Figure 28. I²S Pipeline Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission.
This Mode Is Also Available in the ADC Serial Data Port.)
Rev. E | Page 29 of 32