SSM2518 Datasheet, PDF (28/48 Pages) Analog Devices – Digital Input Stereo, 2 W, Class-D

SSM2518
SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL REGISTER
Address: 0x02, Reset: 0x02, Name: Serial_Interface_Sample_Rate_Control
Data Sheet
Table 15. Bit Descriptions for Serial_Interface_Sample_Rate_Control
Bits Bit Name
Settings Description
7
RESERVED
Reserved.
[6:5] SDATA_FMT
Serial Data Format. Only required if SAI = 000.
00 I²S standard; data is delayed by one BCLK cycle
01 Left justified
10 Right justified, 24-bit data
11 Right justified, 16-bit data
[4:2] SAI
Serial Audio Interface Format.
000 I²S, left justified, or right justified stereo (depending on SDATA_FMT)
001 2-slot TDM
010 4-slot TDM
011 8-slot TDM
100 16-slot TDM
101 Mono PCM
110 Reserved
111 Reserved
[1:0] FS
Manual Sample Rate Selection. Only required if ASR = 1 in Register 0x01.
00 8 kHz to 12 kHz
01 16 kHz to 24 kHz
10 32 kHz to 48 kHz
11 64 kHz to 96 kHz
Reset
0x0
0x0
0x0
0x2
Access
RW
RW
RW
RW
Rev. A | Page 28 of 48